IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 57

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Register Descriptions
Figure 3–26. Typical Avalon-MM Interface TIming for Multiple Reads
Figure 3–27. Typical Avalon-MM Interface TIming for Multiple Writes
3.6. Register Descriptions
© July 2010 Altera Corporation
avalon_writedata[31:0]
avalon_write_data[31:0]
avalon_readdata[31:0]
avalon_writedata[31:0]
avalon_readdata[31:0]
avalon_address[9:0]
avalon_waitrequest
avalon_address[9:0]
avalon_waitrequest
avalon_reset_n
avalon_reset_n
avalon_st_clk
avalon_write
avalon_read
avalon_st_clk
avalon_write
avalon_read
Figure 3–26
Figure 3–27
This section defines the control interface register map.
register, except for the ECC feature management registers which are described in
“ECC Monitoring and Testing” on page
and access columns provide the following information:
■
000
The HW reset column specifies the value after hardware reset, which is controlled
by the reset signal.
00000000
illustrates the timing for reads on the Avalon-MM interface.
illustrates the timing for writes on the Avalon-MM interface.
000
02E
002
003
3–44. In
02C
004
Table
0C0
10-Gbps Ethernet IP Functional Description
Table 3–16
3–16, the HW reset, SW reset
0C1
01B
shows each usable
007
008
01F
3–31