IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 82

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–56
Table 3–56. Top-Level Transceiver Signals (Part 2 of 2)
3.7.2. PMA Reconfiguration
3.7.3. External PHYs
10-Gbps Ethernet IP Functional Description
reconfig_fromgxb[<n>:0]
Note to
(1) <n> = 3 for Stratix II GX, 68 for Stratix IV GX in the soft XAUI implementation, and 17 for the hard XAUI implementation.
(2) <n> = 3 for Stratix II GX, 4 for Arria II GX and Stratix IV GX.
(Note 2)
Table
Signal Name
3–56:
f
f
For additional details about the transceiver signals, refer to the “Stratix II GX
ALT2GXB Ports List” in the
Port List” in Volume 2 of the
List” in Volume 2 of the
For Stratix II GX devices with XAUI, if you turn on Use external reconfiguration
block, you can modify analog properties of the transceiver with an external
reconfiguration block (ALT2GXB_RECONFIG). For Stratix IV or Arria II GX devices
using XAUI, you must include an external reconfiguration block, so this option is
always on. For Arria GX devices, this option is not available. When you use an
external reconfiguration block, you must select the starting channel number.
For more information on the ALT2GXB_RECONFIG megafunction, refer to the
Stratix II GX ALT2GXB_RECONFIG Megafunction User
about the ALTGX_RECONFIG megafunction refer to
Reconfiguration in Arria II GX
The XAUI reconfiguration instantiates the transceiver reconfiguration block. This
block converts Avalon-MM instructions into a format supported by the transceiver
configuration module. In this design example, the relationship between the system
clock and the reconfiguration clock is critical.
3.7.2.1. PHY Loopback
The 10-Gbps Ethernet IP core does not provide a loopback at the PMA interface. If this
feature is critical to your design, you can create a MAC only option and hard XAUI
block separately. The soft XAUI block does not support loopback at the PMA
interface.
3.7.2.2. Reset Controller
The XAUI PHY architecture requires the various resets to be asserted in a specific
sequence. Refer to the device handbook for your device for details. The 10-Gbps
Ethernet IP core provides an example of correct reset sequencing.
If you chose the MAC only 10-Gbps Ethernet variation, you can instantiate either a
PCS Base-X that you have developed or a Base-R PCS in your design and connect this
PCS to the MAC that Altera provides.
Dir
O
1-bit output from PMA. The width depends on the device and also whether
soft or hard XAUI PCS has been selected.
Arria II GX Device
Stratix II GX Transceiver User
Devices.
Stratix IV GX Device
Handbook.
Description
Handbook, or the “Transceiver Port
Guide. For more information
AN 558: Implementing Dynamic
Guide, the “Transceiver
© July 2010 Altera Corporation
10-Gbps Ethernet PHY