IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 58

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–32
Table 3–16. Control Interface Register Map (Part 1 of 7)
10-Gbps Ethernet IP Functional Description
0x000
0x004
0x008
0x00C
0x010
Address
Offset
rev
scratch
command_config
mac_0
mac_1
f
1
■
■
You must perform a software reset before you write to a non-ECC register, then
re-enable the design.
For more information about how to access 64-bit registers, refer to
Counters” on page
Name
The SW reset column specifies the value or influence after a software reset, which
is controlled by the SW_RESET bit in the command_config register.
■
■
The access column indicates whether you can only read a register (RO), write it
(WO) or read and write it (RW).
“—” indicates that reset is not relevant to this register and has no influence.
“X” indicates that the value is unknown, which is typical for memory-based
registers.
3–43.
Revision. This register is divided into
two 16-bit fields:
■
■
Scratch register. Provides a memory
location for user applications to test
the device memory operation.
Command register. The host
processor uses this register to control
and configure the IP core.
32-bit primary address word 0: bits
0–31 of the primary address.
Bit 0 maps to bit 0 of the address, bit
1 maps to bit 1 of the address, and so
on.
32-bit primary address word 1: bits
32–47 of the primary address.
Bits 16–31 are reserved.
Bit 0 maps to bit 32 of the address.
Bits 15:0: IP core revision, set to
0x0702
Bit 31:16: Customer specific
revision, set to 0 during IP core
configuration. This field is
controlled by the parameter
CUST_VERSION defined in the
top level generated for the 10-Gbps
Ethernet IP core instance.
Description
Access
RW
RW
RW
RW
RO
© July 2010 Altera Corporation
0x00000901
HW Reset
0
0
0
0
“64-Bit Statistics
Register Descriptions
bit 0 = 0
bit 1 = 0
Others not
modified
SW Reset
—
—
—
—