IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 24

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–18
Figure 2–7. Clock Domains for the 10-Gbps Ethernet IP Core
2.5.2. Reset Synchronization
2.5.3. Synopsis Design Constraints
Getting Started with the 10-Gbps Ethernet IP
Avalon-ST
Interface
Client
The IP core provides a separate reset pin for each clock domain. The design uses the
following reset and clock pairs:
■
■
■
The reset pins are active low and must be synchronized by their respective clocks
before use.
The timing constraints are provided by the Synopsis Design Constraints File (.sdc). In
this example, tge_91.sdc defines clocks and timing exceptions. The file specifies the
following information:
■
■
■
■
reset_n—resets the sysclk clock domain. sysclk connects to the MAC Tx and
Rx and the MAC side of FIFO interfaces.
avl_st_reset_n—resets the avl_st_clk clock domain. The clock domain is
for the client side of the FIFO or MAC logic.
avalon_reset_n—resets the avalon_clk domain.
All clocks generated from PLLs
Timing uncertainty from clock sources
All clocks that are not generated from PLLs
All asynchronous clock groups
avl_st_clk
domain
Avalon-MM Clock Domain
reconfig_clock Domain
FIFO
Chapter 2: Getting Started with the 10-Gbps Ethernet IP
domain
sysclk
Implementation and Timing Analysis
© July 2010 Altera Corporation
XGMII-like
Interface
64-bit
SDR