IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 37

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

MAC Functional Description
Table 3–3. FIFO or Client MAC Interface Signals (Part 2 of 2)
Figure 3–10. Client or FIFO MAC Tx Interface Timing
3.2.3. MAC – PHY Tx Interface
© July 2010 Altera Corporation
user_tx_data_valid
user_tx_data[63:0]
user_tx_err
user_tx_read
user_tx_mty[2:0]
avalon_st_clk
user_tx_error
user_tx_read
user_tx_eop
user_tx_sop
user_tx_dav
Signal Name
1
Figure 3–10
The PHY side of MAC interfaces implements the XGMII protocol as defined by IEEE
802.3 2005 standard. The standard XGMII implementation consists of 4-lane (32-bit)
wide data bus transitioning at both edges of a 156.25 MHz clock. However, the Altera
IP uses a single data rate (SDR) version of this interface, when connecting a MAC to
an internal PHY.
When you parameterize the 10-Gbps Ethernet IP core to include both Altera MAC
and integrated PHY, the MAC-PHY Tx interface is an SDR version of XGMII. When
you configure the IP core to connect the Altera MAC to an external PHY, the standard
DDR XGMII interface is generated.
In this document, both SDR and DDR interfaces are generally referred to as XGMII
interfaces.
3.2.3.1. Standard DDR XGMII Interface
The DDR XGMII interface consists of a 32-bit data, 4-bit control bus, and a source
synchronous clock.
Dir
O
I
Marks the current client packet as errored. This signal must be asserted by the client
when it asserts the user_tx_eop.
This signal indicates that the Tx MAC is ready to accept data. It is used to apply
backpressure. This signal is deasserted by the MAC when it is inserting CRC or IPG
bytes. The client must stop sending data one clock cycle after this signal is deasserted.
When this signal is asserted, the client may drive data to the MAC on the next clock
cycle. Refer to
illustrates the timing for the client or FIFO Tx interface.
Figure 3–11
Figure
3–10.
illustrates this interface.
6
Description
10-Gbps Ethernet IP Functional Description
5
3–11