IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 23

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started with the 10-Gbps Ethernet IP
Implementation and Timing Analysis
#
#
# 1075559 eth_gen generating packet pkt_type
# 1128847 avl_st_checker : received packet
# 1187559 eth_gen generating packet pkt_type
# 1231247 avl_st_checker : received packet
Testbench tb.custdemo elapsed time 2000 ns
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# 3538447 avl_st_gen generating packet pkt_type
# 3634447 avl_st_gen generating packet pkt_type
# 3730447 avl_st_gen generating packet pkt_type
# 3826447 avl_st_gen generating packet pkt_type
# 3922447 avl_st_gen generating packet pkt_type
#
#
# DONECHECK #1: tb.custdemo, time: 5656 ns
# ***************************************************************
# $$$ End of testbench tb.custdemo at :
# chk_cnt = 1, exp_chk_cnt = 1
# err_cnt = 0, exp_err_cnt = 0
# $$$ Exit status for testbench tb.custdemo : TESTBENCH_STATUS: COMPLETED PASSED
2.5. Implementation and Timing Analysis
2.5.1. Clock Domains
© July 2010 Altera Corporation
Testbench tb.custdemo elapsed time 1000 ns
Testbench tb.custdemo elapsed time 3000 ns
Testbench tb.custdemo elapsed time 4000 ns
Testbench tb.custdemo elapsed time 5000 ns
When you generate a custom 10-Gbps Ethernet IP core, the Quartus II software also
generates files for timing constraints and place and route. When you instantiate your
Ethernet IP core in a complete system design, you can use these scripts as a guide
when creating the timing constraints for your complete system.
You can use the Tcl interface to add constraints to your design. In particular, the
constraints in the tge_91_contraints.tcl file prevent shift registers from converting to
memory, which is important if your design includes the optional ECC functionality.
To add these constraints to your design, type the following command in the
Quartus II Tcl Console window:
The 10-Gbps Ethernet IP core includes at least three clock domains. There is a fourth
clock domain if your design includes the ALTGX_RECONFIG megafunction
discussed in
domains are shown in
clock boundaries. This logic is not shown in
source tge_91_contraints.tcl
“Transceiver Reconfiguration Options” on page
Figure
2–7. The design logic synchronizes signals that cross
5666359
103 -- pkt_size
104 -- pkt_size
100 -- pkt_size
101 -- pkt_size
102 -- pkt_size
103 -- pkt_size
104 -- pkt_size
Figure
2–7.
Getting Started with the 10-Gbps Ethernet IP
2–7. These clock
103
104
100
101
102
103
104
2–17