PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 91

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.4
A device Reset forces all registers to their Reset state.
Thus, the A/D module is turned off and any pending
conversion
registers are unchanged.
12.5
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0 bits of the CCP1CON Register be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with
ADRESH:ADRESL to the desired location).
TABLE 12-3:
© 2008 Microchip Technology Inc.
Name
ADCON0
ADCON1
ADRESH
ADRESL
ANSEL0
ANSEL1
INTCON
PIE1
PIR1
PORTA
PORTB
PORTC
TRISA
TRISB
TRISC
Legend:
minimal
Effects of Reset
Use of the CCP Trigger
x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module.
is
Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result
Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result
TRISB7
TRISC7
ADFM
ANS7
Bit 7
EEIE
EEIF
RB7
RC7
GIE
—
—
—
—
software
aborted.
SUMMARY OF A/D REGISTERS
TRISC6
TRISB6
ADCS2
VCFG
ANS6
Bit 6
ADIE
PEIE
ADIF
RC6
RB6
—
—
—
overhead
The
CCP1IE
CCP1IF
TRISC5
TRISA5
TRISB5
ADCS1
CHS3
ANS5
Bit 5
T0IE
RC5
RA5
RB5
—
ADRESH:ADRESL
(moving
TRISA4
TRISB4
TRISC4
ADCS0
CHS2
ANS4
Bit 4
INTE
C2IE
C2IF
RA4
RB4
RC4
—
the
TRISA3
TRISC3
ANS11
CHS1
ANS3
Bit 3
RAIE
C1IE
C1IF
RA3
RC3
—
—
—
TRISA2
TRISC2
ANS10
OSFIE
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared), then
the “special event trigger” will be ignored by the
module, but will still reset the Timer1 counter. See
Section 8.0 “Capture/Compare/PWM (CCP) Module”
for more information.
OSFIF
CHS0
Bit 2
ANS2
T0IF
RA2
RC2
—
—
—
PIC16F785/HV785
GO/DONE
TMR2IE
TMR2IF
TRISA1
TRISC1
ANS1
ANS9
Bit 1
INTF
RA1
RC1
—
—
—
TMR1IE
TMR1IF
TRISA0
TRISC0
ADON
ANS0
ANS8
Bit 0
RAIF
RA0
RC0
—
—
—
POR, BOR
0000 0000
-000 ----
xxxx xxxx
xxxx xxxx
1111 1111
---- 1111
0000 0000
0000 0000
0000 0000
--xx xxxx
xxxx ----
xxxx xxxx
--11 1111
1111 ----
1111 1111
Value on
DS41249E-page 89
other Resets
Value on all
0000 0000
-000 ----
uuuu uuuu
uuuu uuuu
1111 1111
---- 1111
0000 0000
0000 0000
0000 0000
--uu uuuu
uuuu ----
uuuu uuuu
--11 1111
1111 ----
1111 1111
A/D