PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 87

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.7
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Table 19-16 and
Table 19-17. After this sample time has elapsed, the
A/D conversion can be started.
These steps should be followed for an A/D conversion:
1.
2.
3.
4.
5.
6.
7.
© 2008 Microchip Technology Inc.
Configure the A/D module:
• Configure analog/digital I/O (ANSx)
• Select A/D conversion clock in the ADCON1
• Configure voltage reference in the ADCON0
• Select A/D input channel in the ADCON0
• Select result format in the ADCON0 Register
• Turn on A/D module in the ADCON0 Register
Configure A/D interrupt (if desired):
• Clear ADIF bit of the PIR1 Register
• Set ADIE bit of the PIE1 Register
• Set PEIE and GIE bits of the INTCON Regis-
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0<1>)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
• Waiting for the A/D interrupt
Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as T
required before the next acquisition starts.
Register
Register
Register
ter
(with interrupts disabled); OR
CONFIGURING THE A/D
AD
. A minimum wait of 2 T
AD
is
EXAMPLE 12-1:
;This code block configures the A/D
;for polling, Vdd reference, R/C clock
;and RA0 input.
;
;Conversion start and wait for complete
;polling code included.
;
BCF
BSF
MOVLW
MOVWF
BSF
BSF
BCF
MOVLW
MOVWF
CALL
BSF
BTFSC
GOTO
MOVF
MOVWF
BSF
MOVF
BCF
MOVWF
PIC16F785/HV785
STATUS,RP1
STATUS,RP0
B’01110000’ ;A/D RC clock
ADCON1
TRISA,0
ANSEL0,0
STATUS,RP0
B’10000001’ ;Right, Vdd Vref, AN0
ADCON0
SampleTime
ADCON0,GO
ADCON0,GO
$-1
ADRESH,W
RESULTHI
STATUS,RP0
ADRESL,W
STATUS,RP0
RESULTLO
A/D CONVERSION
;Bank 1
;
;Set RA0 to input
;Set RA0 to analog
;Bank 0
;Wait min sample time
;Start conversion
;Is conversion done?
;No, test again
;Read upper 2 bits
;Bank 1
;Read lower 8 bits
;Bank 0
DS41249E-page 85