PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 14

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F785/HV785
TABLE 2-3:
DS41249E-page 12
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Addr
1:
2:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
OSCCON
OSCTUNE
ANSEL0
PR2
ANSEL1
WPUA
IOCA
REFCON
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
Name
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled, otherwise this
bit resets to ‘1’.
RA3 pull-up is enabled when MCLRE is ‘1’ in Configuration Word.
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PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Timer2 Module Period Register
Unimplemented
Unimplemented
EEPROM Control Register 2 (not a physical register)
Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result
C1VREN
EEADR7
EEDAT7
TRISB7
TRISC7
RAPU
ANS7
EEIE
Bit 7
IRP
GIE
—
—
—
—
—
—
—
—
—
—
—
C2VREN
EEADR6
EEDAT6
INTEDG
TRISB6
TRISC6
ADCS2
IRCF2
ANS6
PEIE
ADIE
Bit 6
RP1
—
—
—
—
—
—
—
—
—
EEADR5
EEDAT5
CCP1IE
TRISA5
TRISB5
TRISC5
WPUA5
ADCS1
IRCF1
IOCA5
BGST
T0CS
ANS5
Bit 5
T0IE
VRR
RP0
—
—
—
—
—
Write Buffer for Upper 5 bits of Program Counter
SBOREN
EEADR4
EEDAT4
TRISA4
TRISB4
TRISC4
WPUA4
ADCS0
IRCF0
IOCA4
VRBB
TUN4
ANS4
T0SE
Bit 4
INTE
C2IE
TO
—
—
—
WPUA3
EEADR3
EEDAT3
WRERR
TRISC3
OSTS
TRISA3
ANS11
IOCA3
VREN
TUN3
ANS3
Bit 3
RAIE
C1IE
PSA
VR3
PD
—
—
—
(1)
(2)
EEADR2
EEDAT2
TRISC2
WPUA2
TRISA2
OSFIE
ANS10
IOCA2
WREN
VROE
TUN2
ANS2
Bit 2
T0IF
HTS
PS2
VR2
—
—
—
Z
EEADR1
TMR2IE
EEDAT1
TRISA1
TRISC1
WPUA1
CVROE
IOCA1
ANS1
TUN1
ANS9
Bit 1
INTF
POR
VR1
PS1
LTS
WR
DC
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© 2008 Microchip Technology Inc.
EEADR0
EEDAT0
TMR1IE
TRISA0
TRISC0
WPUA0
IOCA0
TUN0
ANS0
ANS8
RAIF
Bit 0
BOR
SCS
VR0
PS0
RD
—
—
—
C
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
1111 ----
1111 1111
---0 0000
0000 000x
0000 0000
---1 --qq
-110 q000
---0 0000
1111 1111
1111 1111
---- 1111
--11 1111
--00 0000
--00 000-
000- 0000
0000 0000 103,114
0000 0000 103,114
---- x000 104,114
---- ---- 104,114
xxxx xxxx
-000 ----
POR, BOR
Value on
—
—
—
—
—
22,114
17,114
21,114
15,114
22,114
35,114
42,114
45,114
21,114
17,114
18,114
20,114
33,114
28,114
82,114
55,114
82,114
36,114
37,114
73,114
72,114
81,114
84,114
Page
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