PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 56

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F785/HV785
6.5
If control bit T1SYNC of the T1CON Register is set, the
external clock input is not synchronized. The timer con-
tinues to increment asynchronous to the internal phase
clocks. The timer will continue to run during Sleep and
can generate an interrupt on overflow, which will wake-
up the processor. However, special precautions in
software
(Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
6.5.1
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
TABLE 6-1:
DS41249E-page 54
Name
ANSEL0
CM2CON1
INTCON
PIE1
PIR1
T1CON
TMR1L
TMR1H
Legend:
Note:
Timer1 Operation in
Asynchronous Counter Mode
are
The ANSEL0 (91h) register must be initial-
ized to configure an analog channel as a
digital input. Pins configured as analog
inputs will read ‘0’.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
– x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
MC1OUT MC2OUT
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1GINV
ANS7
Bit 7
EEIE
EEIF
GIE
needed
REGISTERS ASSOCIATED WITH TIMER1
TMR1GE T1CKPS1
ANS6
PEIE
ADIE
ADIF
Bit 6
to
read/write
CCP1IE
CCP1IF
ANS5
Bit 5
T0IE
—
T1CKPS0
ANS4
the
INTE
Bit 4
C2IE
C2IF
—
timer
T1OSCEN
ANS3
RAIE
Bit 3
C1IE
C1IF
—
T1SYNC
OSFIE
OSFIF
6.6
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN of the T1CON Register.
The oscillator is a low power oscillator rated for 32.768
kHz. It will continue to run during Sleep. It is primarily
intended for a 32.768 kHz tuning fork crystal.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is also the LP oscillator or is
derived from the internal oscillator. As with the system
LP oscillator, the user must provide a software time
delay to ensure proper oscillator start-up.
Sleep mode will not disable the system clock when the
system clock and Timer1 share the LP oscillator.
TRISA<5> and TRISA<4> bits are set when the Timer1
oscillator is enabled. RA5 and RA4 read as ‘0’ and
TRISA<5> and TRISA<4> bits read as ‘1’.
6.7
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
• Timer1 of the T1CON Register must be on
• TMR1IE bit of the PIE1 Register must be set
• PEIE bit of the INTCON Register must be set
The device will wake-up on an overflow. If the GIE bit of
the INTCON Register is set, the device will wake-up
and jump to the Interrupt Service Routine (0004h) on
an overflow. If the GIE bit is clear, execution will con-
tinue with the next instruction.
ANS2
Bit 2
T0IF
—
Note:
TMR1CS
Timer1 Oscillator
Timer1 Operation During Sleep
TMR2IE
TMR2IF
T1GSS
ANS1
Bit 1
INTF
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
TMR1ON
C2SYNC
TMR1IE
TMR1IF
ANS0
Bit 0
RAIF
© 2008 Microchip Technology Inc.
1111 1111
00-- --10
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
POR, BOR
Value on
other Resets
Value on all
1111 1111
00-- --10
0000 0000
0000 0000
0000 0000
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