PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 38

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F785/HV785
REGISTER 4-2:
4.2
Every PORTA pin on the PIC16F785/HV785 has an
interrupt-on-change option and a weak pull-up option.
The next three sections describe these functions.
REGISTER 4-3:
DS41249E-page 36
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
Note 1: TRISA<3> always reads ‘1’.
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
U-0
U-0
—
—
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
3: The RA3 pull-up is automatically enabled when configured as MCLR in the Configuration Word.
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
Additional Pin Functions
(TRISA = 0).
Unimplemented: Read as ‘0’
TRISA<5:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Unimplemented: Read as ‘0’
WPUA<5:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
U-0
U-0
—
—
TRISA: PORTA TRI-STATE REGISTER
WPUA: WEAK PULL-UP REGISTER
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
TRISA5
WPUA5
R/W-1
R/W-1
(2)
(4)
WPUA4
TRISA4
R/W-1
R/W-1
(2)
(4)
(1), (2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRISA3
WPUA3
R/W-1
4.2.1
Each of the PORTA pins has an individually configurable
internal weak pull-up. Control bits WPUAx enable or
disable each pull-up. Refer to Register 4-3. Each weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
Power-on Reset by the RAPU bit in the (OPTION
Register. The weak pull-up on RA3 is automatically
enabled when RA3 is configured as MCLR.
R-1
(1)
(3)
WEAK PULL-UPS
TRISA2
WPUA2
R/W-1
R/W-1
(1)
© 2008 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
WPUA1
TRISA1
R/W-1
R/W-1
TRISA0
WPUA0
R/W-1
R/W-1
bit 0
bit 0