PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 102

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F785/HV785
13.9
The Two-Phase PWM module may be configured to
operate in a Complementary Output mode where PH1
and PH2 are always 180 degrees out-of-phase (see
Figure 13-5).
available and are selected by the COMOD<1:0> bits in
the PWMCON1 register (see Register 13-5). The differ-
ence between the modes is the method by which the
PH1 and PH2 outputs switch from the active to the
inactive state during the PWM period.
In Complementary mode, there are three methods by
which the duty cycle can be controlled. These modes
are selected with the COMOD<1:0> bits (see
Register 13-5). In each of these modes, the duty cycle
is started when the pwm_count = PWMPH1<4:0> and
terminates on one of the following:
• Feedback through C1 or C2
• When the pwm_count equals PWMPH1<4:0>
• Combined feedback and pwm_count match
When COMOD<1:0> = 01, the duty cycle is controlled
only by feedback through comparator C1 or C2. In this
mode, the active drive cycle starts when pwm_count
equals PWMPH1<4:0> and terminates when compara-
tor
PWMPH1<5> = 1) or when comparator C2 output goes
high (if enabled by PWMPH1<6> = 1).
When COMOD<1:0> = 10, the duty cycle is controlled
only by the PWM Phase counter. In this mode, the
active drive cycle starts when the pwm_count equals
PWMPH1<4:0> and terminates when the pwm_count
equals PWMPH2<4:0>. For example, free running
50% duty cycle can be accomplished by setting
COMOD<1:0> = 10 and choosing appropriate values
for PWMPH1<4:0> and PWMPH2<4:0>.
When COMOD<1:0> = 11, the duty cycle is controlled
by the phase counter or feedback through comparator
C1 or C2. For example, in this mode, the maximum
duty
PWMPH1<4:0> (duty cycle start) and PWMPH2<4:0>
(duty cycle end). The duty cycle can be terminated
earlier than the maximum by feedback through
comparator C1 or C2.
13.9.1
The Complementary Output mode facilitates driving
series connected MOSFET drivers by providing dead
band drive timing between each phase output (see
Figure 13-6). Dead band times are selectable by the
CMDLY<4:0> bits of the PWMCON1 register. Delays
from 0 to 155 nanoseconds (typical) with a resolution of
5 nanoseconds (typical) are available.
DS41249E-page 100
C1’s
cycle
Complementary Output Mode
DEAD BAND CONTROL
output
is
Three
determined
goes
complementary
high
by
(if
the
enabled
modes
values
are
by
of
13.9.2
Overlap timing can be accomplished by configuring the
Complementary mode for the desired output polarity
and overlap time (as dead time) then swapping the out-
put connections and inverting the outputs. For exam-
ple, to configure a complementary drive for 55 ns of
overlap and an active-high drive output on PH1 and an
active-low drive output on PH2, set the PWM control
registers as follows:
• Connect PH1 driver to PH2 output
• Connect PH2 driver to PH1 output
• Initialize PORTC<1> to 1 (PH2 driver off)
• Initialize PORTC<4> to 0 (PH1 driver off)
• Set TRISC<1,4> to 0 for output
• Set PWMPH1<POL> to 1 (Inverted PH1)
• Set PWMPH2<POL> to 1 (Non-Inverted PH2)
• Set PWMCON1 for 55 ns delay and desired
• Set PWMCON0 desired SYNC and auto-shutdown
13.9.3
During shutdown the PH1 and PH2 complementary
outputs are forced to their inactive states (see
Figure 13-5). When shutdown ceases the PWM out-
puts revert to their start-up states for the first cycle
which is PH1 inactive (output undriven) and PH2 active
(output driven).
termination (comparator, count or both)
configuration and to enable PH1 and PH2
OVERLAP CONTROL
SHUTDOWN IN COMPLEMENTARY
MODE
© 2008 Microchip Technology Inc.