PIC16F785-E/SS Microchip Technology, PIC16F785-E/SS Datasheet - Page 110

• Manufacturer Part Number: PIC16F785-E/SS
• Description: 20 PIN, 3.5 KB STD FLASH, 128 RAM, 18 I/O PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPAC162060 - HEADER INTRFC MPLAB ICD2 20PIN
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F785/HV785
REGISTER 15-1:
DS41249E-page 108
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 13-12
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note
R/P-0
CPD
U-0
—
1:
2:
3:
4:
5:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
Program memory bulk erase must be performed to turn off code protection.
The entire data EEPROM will be erased when the code protection is turned off.
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
If the HS, XT, or LP oscillator fails In Fail-safe mode the Watchdog time-out can occur only once after which it will be disabled
until the oscillator is restored.
FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
BOREN<1:0>: Brown-out Reset Selection bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit (PCON<4>)
00 = BOR disabled
CPD: Data Code Protection bit
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: RA3/MCLR pin function select bit
1 = RA3/MCLR pin function is MCLR
0 = RA3/MCLR pin function is digital input, MCLR internally tied to V
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)
FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on
100 = INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on
011 = EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, CLKIN on RA5/T1CKI/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN
R/P-1
U-0
CP
—
CONFIG: CONFIGURATION WORD
RA5/T1CKI/OSC1/CLKIN
RA5/T1CKI/OSC1/CLKIN
W = Writable bit
‘1’ = Bit is set
MCLRE
R/P-1
U-0
(2)
—
(2), (3)
(5)
PWRTE
R/P-1
U-0
—
(4)
(5)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FCMEN
WDTE
R/P-0
R/P-1
DD
FOSC2
R/P-0
R/P-1
IESO
© 2008 Microchip Technology Inc.
x = Bit is unknown
BOREN1
FOSC1
R/P-1
R/P-1
(5)
(5)
BOREN0
FOSC0
R/P-1
R/P-1
(5)
bit 8
bit 0