AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 72

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
2- 56
FlashROM
Fusion devices have 1 kbit of on-chip nonvolatile flash memory that can be read from the FPGA core
fabric. The FlashROM is arranged in eight banks of 128 bits during programming. The 128 bits in each
bank are addressable as 16 bytes during the read-back of the FlashROM from the FPGA core
45).
The FlashROM can only be programmed via the IEEE 1532 JTAG port. It cannot be programmed directly
from the FPGA core. When programming, each of the eight 128-bit banks can be selectively
reprogrammed. The FlashROM can only be reprogrammed on a bank boundary. Programming involves
an automatic, on-chip bank erase prior to reprogramming the bank. The FlashROM supports a
synchronous read and can be read on byte boundaries. The upper three bits of the FlashROM address
from the FPGA core define the bank that is being accessed. The lower four bits of the FlashROM
address from the FPGA core define which of the 16 bytes in the bank is being accessed.
The maximum FlashROM access clock is 20 MHz.
FlashROM access cycle—the address has to be set up on the rising edge of the clock for DOUT to be
valid on the next falling edge of the clock.
If the address is unchanged for two cycles:
If the address unchanged for three cycles:
Figure 2-45 • FlashROM Architecture
•
•
•
•
•
•
D0 becomes invalid 10 ns after the second rising edge of the clock.
D0 becomes valid again 10 ns after the second falling edge.
D0 becomes invalid 10 ns after the second rising edge of the clock.
D0 becomes valid again 10 ns after the second falling edge.
D0 becomes invalid 10 ns after the third rising edge of the clock.
D0 becomes valid again 10 ns after the third falling edge.
7
6
5
4
3
2
1
0
15
Byte Number in Bank
14
13
12
11
10
R e visio n 1
9
4 LSB of ADDR (READ)
8
Figure 2-46
7
6
5
shows the timing behavior of the
4
3
2
1
0
(Figure 2-