AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 40

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
Notes:
1. Visit the
2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the Fusion family.
3. Refer to the
Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macro
Table 2-11 • Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros
2- 24
Notes:
1. This is the default macro. For more details, refer to the
2. The BLVDS and M-LVDS standards are supported with CLKBUF_LVDS.
section on page 2-29
Actel website
PADN
PADP
Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide
Input LVDS/LVPECL Macro
PAD
Clock Source
INBUF
for signal descriptions.
for future application notes concerning dynamic PLL reconfiguration. Refer to the
2
Macro
Y
Y
CLKBUF_LVCMOS33
CLKBUF_LVCMOS18
CLKBUF_LVCMOS15
CLKBUF_LVCMOS5
CLKBUF_LVPECL
CLKBUF Macros
CLKBUF_LVDS
CLKA
EXTFB
POWERDOWN
OADIVRST
OADIVHALF
OADIV[4:0]
OAMUX[2:0]
DLYGLA[4:0]
OBDIV[4:0]
OBMUX[2:0]
DLYYB[4:0]
DLYGLB[4:0]
OCDIV[4:0]
OCMUX[2:0]
DLYYC[4:0]
DLYGLC[4:0]
FINDIV[6:0]
FBDIV[6:0]
FBDLY[4:0]
FBSEL[1:0]
XDLYSEL
VCOSEL[2:0]
Clock Conditioning
CLKBUF_PCI
Fusion, IGLOO/e and ProASIC3/E Macro Library
R e visio n 1
LOCK
GLA
GLB
GLC
2
YB
YC
for more information.
1
GLA
or
GLA and (GLB or YB)
or
GLA and (GLC or YC)
or
GLA and (GLB or YB) and
(GLC or YC)
Output
Guide.
"PLL Macro"