AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 115

FPGA - Field Programmable Gate Array 250K System Gates

AFS250-FGG256

Manufacturer Part Number
AFS250-FGG256
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet

Specifications of AFS250-FGG256

Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
114
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AFS250-FGG256
Manufacturer:
Actel
Quantity:
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AFS250-FGG256
Manufacturer:
ACTEL
Quantity:
6 800
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Microsemi SoC
Quantity:
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Part Number:
AFS250-FGG256I
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Quantity:
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Actel Fusion Family of Mixed Signal FPGAs
Terminology
Resolution
Resolution defines the smallest temperature change Fusion Temperature Monitor can resolve. For ADC
configured as 8-bit mode, each LSB represents 4°C, and 1°C per LSB for 10-bit mode. With 12-bit mode,
the Temperature Monitor can still only resolve 1°C due to Temperature Monitor design.
Offset
The Fusion Temperature Monitor has a systematic offset of +5°C, excluding error due board resistance
and ideality factor of the external diode, between the operation range of –40°C to +85°C. For instance,
25°C will be read by the Temperature Monitor as 30°C plus error. The user can remove any offset error
through hardware or software during the calibration routine.
Analog-to-Digital Converter Block
At the heart of the Fusion analog system is a programmable Successive Approximation Register (SAR)
ADC. The ADC can support 8-, 10-, or 12-bit modes of operation. In 12-bit mode, the ADC can resolve
500 ksps. All results are MSB-justified in the ADC. The input to the ADC is a large 32:1 analog input
multiplexer. A simplified block diagram of the Analog Quads, analog input multiplexer, and ADC is shown
in
Figure
2-80. The ADC offers multiple self-calibrating modes to ensure consistent high performance
both at power-up and during runtime.
R e v i s i o n 1
2- 99

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