AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 246

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
128-Bit AES Decryption
The 128-bit AES standard (FIPS-197) block cipher is the National Institute of Standards and Technology
(NIST) replacement for DES (Data Encryption Standard FIPS46-2). AES has been designed to protect
sensitive government information well into the 21st century. It replaces the aging DES, which NIST
adopted in 1977 as a Federal Information Processing Standard used by federal agencies to protect
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sensitive, unclassified information. The 128-bit AES standard has 3.4 × 10
possible 128-bit key
variants, and it has been estimated that it would take 1,000 trillion years to crack 128-bit AES cipher text
using exhaustive techniques. Keys are stored (securely) in Fusion devices in nonvolatile flash memory.
All programming files sent to the device can be authenticated by the part prior to programming to ensure
that bad programming data is not loaded into the part that may possibly damage it. All programming
verification is performed on-chip, ensuring that the contents of Fusion devices remain secure.
AES decryption can also be used on the 1,024-bit FlashROM to allow for secure remote updates of the
FlashROM contents. This allows for easy, secure support for subscription model products. See the
application note
for more details.
Fusion Security
AES for Flash Memory
AES decryption can also be used on the flash memory blocks. This allows for the secure update of the
flash memory blocks. During runtime, the encrypted data can be clocked in via the JTAG interface. The
data can be passed through the internal AES decryption engine, and the decrypted data can then be
stored in the flash memory block.
Programming
Programming can be performed using various programming tools, such as Silicon Sculptor II (BP Micro
Systems) or FlashPro3 (Actel).
The user can generate STP programming files from the Designer software and can use these files to
program a device.
Fusion devices can be programmed in-system. During programming, V
is needed in order to
CCOSC
power the internal 100 MHz oscillator. This oscillator is used as a source for the 20 MHz oscillator that is
used to drive the charge pump for programming.
ISP
Fusion devices support IEEE 1532 ISP via JTAG and require a single V
voltage of 3.3 V during
PUMP
programming. In addition, programming via a microcontroller in a target system can be achieved. Refer to
the standard or the "In-System Programming (ISP) of Actel's Low Power Flash Devices Using
FlashPro4/3/3X" chapter of the
for more details.
Fusion FPGA Fabric User’s Guide
JTAG IEEE 1532
Programming with IEEE 1532
Fusion devices support the JTAG-based IEEE1532 standard for ISP. As part of this support, when a
Fusion device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by keeping
the global IO_EN signal deactivated, which also has the effect of disabling the input buffers.
Consequently, the SAMPLE instruction will have no effect while the Fusion device is in this
PLUS®
unprogrammed state—different behavior from that of the ProASIC
device family. This is done
because SAMPLE is defined in the IEEE1532 specification as a noninvasive instruction. If the input
buffers were to be enabled by SAMPLE temporarily turning on the I/Os, then it would not truly be a
noninvasive instruction. Refer to the standard or the"In-System Programming (ISP) of Actel's Low Power
Flash Devices Using FlashPro4/3/3X" chapter of the
for more details.
Fusion FPGA Fabric User’s Guide
Boundary Scan
Fusion devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture and
the set of mechanisms for boundary scan testing. The basic Fusion boundary scan logic circuit is
composed of the test access port (TAP) controller, test data registers, and instruction register
(Figure 2-
144 on page
2-232). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction
(Table 2-182 on page
2-232).
Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input),
TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS, TDI,
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