AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 48

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
2- 32
The NGMUX macro is simplified to show the two clock options that have been selected by the
GLMUXCFG[1:0] bits.
are connected to CLK0 and CLK1 and are controlled by GLMUXSEL[1:0] to determine which signal is to
be passed through the MUX.
Figure 2-25 • NGMUX Macro
The sequence of switching between two clock sources (from CLK0 to CLK1) is as follows
For examples of NGMUX operation, refer to the
Figure 2-26 • NGMUX Waveform
•
•
•
•
•
GLMUXSEL[1:0] transitions to initiate a switch.
GL drives one last complete CLK0 positive pulse (i.e., one rising edge followed by one falling
edge).
From that point, GL stays Low until the second rising edge of CLK1 occurs.
At the second CLK1 rising edge, GL will begin to continuously deliver the CLK1 signal.
Minimum t
GLMUXSEL[1:0]
sw
= 0.05 ns at 25°C (typical conditions)
Figure 2-25
CLK0
CLK1
CLK0
CLK1
GL
illustrates the NGMUX macro. During design, the two clock sources
R e visio n 1
GLMUXSEL[1:0]
Fusion FPGA Fabric User’s
t
SW
GL
Guide.
(Figure
2-26):