AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 14
![FPGA - Field Programmable Gate Array 250K System Gates](/photos/16/15/161503/landingpageactelfusion-2_sml.jpg)
AFS250-FGG256
Manufacturer Part Number
AFS250-FGG256
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS250-FGG256
Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
114
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
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Part Number:
AFS250-FGG256
Manufacturer:
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ACTEL
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Fusion Device Family Overview
1 - 8
standards. In the family’s larger devices, the north bank is divided into two banks of digital Pro I/Os,
supporting a wide variety of single-ended, differential, and voltage-referenced I/O standards.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following applications:
VersaTiles
The Fusion core consists of VersaTiles, which are also used in the successful Actel ProASIC3 family. The
Fusion VersaTile supports the following:
Refer to
Figure 1-2 • VersaTile Configurations
X1
X2
X3
LUT-3 Equivalent
•
•
•
•
•
•
Single-Data-Rate (SDR) applications
Double-Data-Rate (DDR) applications—DDR LVDS I/O for chip-to-chip communications
Fusion banks support LVPECL, LVDS, BLVDS, and M-LVDS with 20 multi-drop points.
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set and optional enable
LUT-3
Figure 1-2
for the VersaTile configuration arrangement.
Y
D-Flip-Flop with Clear or Set
Data
CLK
CLR
D-FF
R e vi s i o n 1
Y
Enable D-Flip-Flop with Clear or Set
Enable
Data
CLK
CLR
D-FFE
Y
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