SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 9

• Manufacturer Part Number: SPEAR320-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR320-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr320
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 102
• Number Of Timers: 4
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10843

SPEAr320
2
Main features
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
ARM926EJ-S 32-bit RISC CPU, up to 333 MHz
–
–
–
–
32-KByte on-chip BootRom
8-KByte on-chip SRAM
External DRAM memory interface:
–
–
Serial memory interface
SDIO interface supporting SPI, SD1, SFD4 and SD8 modes
8/16-bits NAND Flash controller (FSMC)
External memory interface (EMI) for connecting NOR Flash or FPGAs
Boot capability from NAND Flash, serial/parallel NOR Flash
Boot and field upgrade capability from USB
High performance 8-channel DMA controller
2x Ethernet MAC 10/100 Mbps with MII/SMII PHY interface
Two USB2.0 host (high-full-low speed) with integrated PHY transceiver
One USB2.0 device (high-full-low speed) with integrated PHY transceiver
2x CAN 2.0 interfaces
Up to 102 GPIOs with interrupt capability
Up to 4 PWM outputs
3x SSP master/slave (supporting Motorola, Texas instruments, National semiconductor
protocols) up to 41.5 Mbps
Standard Parallel Port (SPP device implementation)
2x I
3x UART: UART0 (up to 3 Mbps) with hardware flow control and modem interface,
UART1 (up to 7 Mbps) with hardware flow control (in some operating modes) and
UART2 (up to 7 Mbps) with software flow control
ADC 10-bit, 1 Msps 8 inputs/1-bit DAC
JPEG CODEC accelerator 1 clock/pixel
Color LCD interface (up to 1024X768, 24-bits CLCD controller, TFT and STN panels)
Touchscreen support
Crypto accelerator (DES/3DES/AES/SHA1)
Advanced power saving features
–
–
2
C master/slave interface (slow- fast-high speed, up to 1.2Mb/s)
16 Kbytes of instruction cache, 16 Kbytes of data cache
3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code
density, byte Java mode (Jazelle™) for direct execution of Java code.
Tightly Coupled Memory
AMBA bus interface
8/16-bit (mobile DDR@166 MHz)
8/16-bit (DDR2@333 MHz)
Normal, Slow, Doze and Sleep modes CPU clock with software-programmable
frequency
Enhanced dynamic power-domain management
Doc ID 16755 Rev 4
Main features
9/76