SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 12

• Manufacturer Part Number: SPEAR320-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR320-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr320
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 102
• Number Of Timers: 4
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10843

Architecture overview
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The ARM CPU and is clocked at a frequency up to 333 MHz. It has a 16-Kbyte instruction
cache, a 16-Kbyte data cache, and features a memory management unit (MMU) which
makes it fully compliant with Linux and VxWorks operating systems.
It also includes an embedded trace module (ETM Medium+) for real-time CPU activity
tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed
trace mode, with normal or half-rate clock.
Embedded memory units
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Mobile DDR/DDR2 memory controller
SPEAr320 integrates a high performance multi-channel memory controller able to support
low power Mobile DDR and DDR2 double data rate memory devices. The multi-port
architecture ensures memory is shared efficiently among different high-bandwidth client
modules.
It has 6 internal ports. One of them is reserved for register access during the controller
initialization while the other five are used to access the external memory.
It also includes the physical layer (PHY) and DLLs for fine tuning the timing parameters to
maximize the data valid windows at different frequencies.
Serial memory interface
SPEAr320 provides a serial memory interface (SMI), acting as an AHB slave interface (32-,
16- or 8-bit) to SPI-compatible off-chip memories.
These serial memories can be used either as data storage or for code execution.
Main features:
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32 Kbytes of BootROM
8 Kbytes of SRAM
Supports the following SPI-compatible Flash and EEPROM devices:
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Acts always as a SPI master and up to 2 SPI slave memory devices are supported
(with separate chip select signals), with up to 16 MB address space each
SMI clock signal (SMICLK) is generated by SMI (and input to all slaves) using a clock
provided by the AHB bus
SMICLK can be up to 50 MHz in fast read mode (or 20 MHz in normal mode). It can be
controlled by a programmable 7-bit prescaler allowing up to 127 different clock
frequencies.
STMicroelectronics M25Pxxx, M45Pxxx
STMicroelectronics M95xxx, except M95040, M95020 and M95010
ATMEL AT25Fxx
YMC Y25Fxx
SST SST25LFxx
Doc ID 16755 Rev 4
SPEAr320