SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 56

• Manufacturer Part Number: SPEAR320-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR320-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr320
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 102
• Number Of Timers: 4
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10843

Timing requirements
Note:
7.4
56/76
1
2
3
The timings shown in
so the values present in the three tables here above have been calculated using the
minimum programmable values of :
IC_HS_SCL_HCNT=19 and IC_HS_SCL_LCNT=53 registers (for High-Speed mode);
IC_FS_SCL_HCNT=99 and IC_FS_SCL_LCNT=215 registers (for Fast-Speed mode);
IC_SS_SCL_HCNT=664 and IC_SS_SCL_LCNT=780 registers (for Standard-Speed
mode).
These minimum values depend on the AHB clock frequency, which is 166 MHz.
A device may internally require a hold time of at least 300 ns for the SDA signal (referred to
the V
(Please refer to the I
in the I
MHz). This time may be insufficient for some slave devices. A few slave devices may not
receive the valid address due to the lack of SDA hold time and will not acknowledge even if
the address is valid. If the SDA data hold time is insufficient, an error may occur.
Workaround: If a device needs more SDA data hold time than one clock cycle, an RC delay
circuit is needed on the SDA line as illustrated in the following figure:
Figure 20. RC delay circuit
For example, R=K and C = 200 pF.
FSMC timing characteristics
The characterization timing is done using primetime considering an output load of 3 pF on
the data, 15 pF on NF_CE, NF_RE and NF_WE and 10 pF on NF_ALE and NF_CLE.
The operating conditions are V= 0.90 V, T=125 °C in worst case and V=1.10 V, T= 40 °C in
best case.
IHmin
2
C controller of SPEAr320 is one-clock cycle based (6 ns with the HCLK clock at 166
of the SCL signal) to bridge the undefined region of the falling edge of SCL
2
C Bus Specification v3-0 Jun 2007). However, the SDA data hold time
Figure 19.
Doc ID 16755 Rev 4
depend on the programmed value of T
SCLHigh
and T
SPEAr320
SCLLow,