SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet
SPEAR320-2
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SPEAR320-2 Summary of contents
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... The SPEAr320 embedded MPU is configurable for a range of industrial and consumer applications such as: ■ Programmable logic controllers ■ Factory automation ■ Printers Table 1. Order code SPEAR320-2 Doc ID 16755 Rev 4 SPEAr320 LFBGA289 ( 1.7 mm) Device summary Temp Package Packing range, C LFBGA289 - (15x15 mm, pitch 0 ...
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... Parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.17 Synchronous serial ports (SSP 3.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.19 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.19.1 3.19.2 3.19.3 3.20 JPEG CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.21 Cryptographic co-processor (C3 3.22 8-channel ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.23 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.23.1 2/76 UART0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Doc ID 16755 Rev 4 SPEAr320 ...
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... SPEAr320 3.23.2 3.24 Vectored interrupt controller (VIC 3.25 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.26 PWM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.28 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 Dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 Shared I/O pins (PL_GPIOs 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4 ...
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... CLCD timing characteristics direct clock . . . . . . . . . . . . . . . . . . . . . . . . 52 CLCD timing characteristics divided clock . . . . . . . . . . . . . . . . . . . . . . . 53 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 MII receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SPI master mode timings (clock phase = SPI master mode timings (clock phase = Doc ID 16755 Rev 4 SPEAr320 ...
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... Table 9. PL_GPIO pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 10. PL_GPIO multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11. Table shading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 12. Ball sharing during debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 13. SPEAr320 main memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 14. Reconfigurable array subsystem memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 15. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 16. Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 17. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 18. ...
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... Switching characteristics over recommended operating conditions for SPI master mode (clock phase =1 )69 Table 49. UART transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 50. UART receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 51. 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 52. LFBGA289 ( 1.7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 53. Thermal resistance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6/76 Doc ID 16755 Rev 4 SPEAr320 ...
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... SPEAr320 List of figures Figure 1. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Typical system architecture using SPEAr320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. Typical SMII system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 4. Hierarchical multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 5. Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 6. Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 7. DDR2 Read cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 8. DDR2 Read cycle path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 9. DDR2 Write cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 10 ...
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... Description 1 Description The SPEAr320 is a member of the SPEAr family of embedded MPUs, optimized for industrial automation and consumer applications based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in applications where high computation performance is required. In addition, SPEAr320 has an MMU that allows virtual memory management -- making the system compliant with Linux operating system. It also offers data cache instruction cache, JTAG and ETM (Embedded Trace Macrocell ...
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... SPEAr320 2 Main features ● ARM926EJ-S 32-bit RISC CPU 333 MHz – 16 Kbytes of instruction cache, 16 Kbytes of data cache – 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code density, byte Java mode (Jazelle™) for direct execution of Java code. – ...
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... JTAG IEEE 1149.1 boundary scan ● ETM functionality multiplexed on primary pins ● Supply voltages – 1.2 V core, 1.8 V/2.5 V DDR, 2.5 V PLLs, 1.5 V RTC and 3.3 V I/Os ● Operating temperature °C ● LFBGA289 ( mm, pitch 0.8 mm) 10/76 Doc ID 16755 Rev 4 SPEAr320 ...
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... CPU ARM 926EJ-S The core of the SPEAr320 is an ARM926EJ-S reduced instruction set computer (RISC) processor. It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes ...
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... It also includes the physical layer (PHY) and DLLs for fine tuning the timing parameters to maximize the data valid windows at different frequencies. 3.4 Serial memory interface SPEAr320 provides a serial memory interface (SMI), acting as an AHB slave interface (32-, 16- or 8-bit) to SPI-compatible off-chip memories. These serial memories can be used either as data storage or for code execution. Main features: ● ...
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... SPEAr320 3.5 External memory interface (EMI) The EMI Controller provides a simple external memory interface that can be used for example to connect to NOR Flash memory or FPGA devices. Main features: ● EMI bus master ● 16 and 8-bit transfers ● Can access 4 different peripherals using CS#, one at a time. ...
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... Boot memory bank configurable at reset using external control pins 3.8 Multichannel DMA controller Within its basic subsystem, SPEAr320 provides a DMA controller (DMAC) able to service independent DMA channels for serial data transfers between single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and peripheral-to-peripheral) ...
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... Jumbo frames 10240 bytes supported ● Configurable Endianess for the DMA Interface (AHB Master) 3.10 MII Ethernet controller SPEAr320 provides an Ethernet MAC 10/100 Universal (commonly referred to as MAC- UNIV), enabling to transmit and receive data over Ethernet in compliance with the IEEE 802.3-2002 standard ...
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... Disabled automatic retransmission mode for time triggered CAN applications 3.12 USB2 host controller SPEAr320 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks: ● EHCI capable of managing high-speed transfers (HS mode, 480 Mbps) ● OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps) ● ...
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... AHB bus ● A USB plug (UPD) detects the connection of a cable. 3.14 CLCD controller SPEAr320 has a color liquid crystal display controller (CLCDC) that provides all the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Main features: ● ...
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... A maximum of 102 GPIOs (PL_GPIOs) are available when part of the embedded or customization IPs are not needed (see Within its basic subsystem, SPEAr320 provides a base General Purpose Input/Output (GPIO) block (basGPIO). The base GPIO block provides 6 programmable inputs or outputs. Each input/output can be controlled in two distinct modes: ● ...
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... SPEAr320 3.17 Synchronous serial ports (SSP) SPEAr320 provides three synchronous serial ports (SSP) that offer a master or slave interface to enable synchronous serial communication with slave or master peripherals Main features: ● Master or slave operation. ● Programmable clock bit rate and prescale. ● Separate transmit and receive first-in, first-out memory buffers, 16-bits wide, 8 locations deep. ● ...
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... Speed Mbps ● Software flow control 3.20 JPEG CODEC SPEAr320 provides a JPEG CODEC with header processing (JPGC), able to decode (or encode) image data contained in the SPEAr320 RAM, from the JPEG (or MCU) format to the MCU (or JPEG) format. 20/76 Doc ID 16755 Rev 4 SPEAr320 ...
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... CODEC core. 3.21 Cryptographic co-processor (C3) SPEAr320 has an embedded Channel Control Coprocessor (C3 high-performance instruction driven DMA based co-processor. It executes instruction flows generated by the host processor. After it has been set-up by the host it runs in a completely autonomous way (DMA data in, data processing, DMA data out), until the completion of all the requested operations ...
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... Watchdog and timer module clock enable 3.23.1 Power saving system mode control Using three mode control bits, the system controller switch the SPEAr320 to any one of four different modes: DOZE, SLEEP, SLOW and NORMAL. ● SLEEP mode: In this mode the system clocks, HCLK and CLK, are disabled and the System Controller clock SCLK is driven by a low speed oscillator (nominally 32768 Hz) ...
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... This method replaces all the other traditional methods of EMI reduction, such as filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal shielding and so on. This gives the customer appreciable cost savings. In sleep mode the SPEAr320 runs with the PLL disabled so the available frequency is 24 MHz or a sub-multiple (/2, /4, /8). 3.24 ...
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... Single-shot mode, an interrupt source is activated, the counter is stopped and the GPT is disabled. 3.26 PWM timers SPEAr320 provides 4 PWM timers. Main features: ● Prescaler to define the input clock frequency to each timer ● Programmable duty cycle from 0% to 100% ● ...
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... SPEAr320 4 Pin description The following tables describe the pinout of the SPEAr320 listed by functional block. List of abbreviations Pull Pull Down 4.1 Required external components 1. DDR_COMP_1V8: place an external 121 kresistor between ball P4 and ball R4 2. USB_TX_RTUNE: connect an external 43.2 k pull-down resistor to ball K5 3. DIGITAL_REXT: place an external 121 k ...
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... USB_DEVICE_VSSA DITH_VSS2V5 MCLK_GND MCLK_GNDSUB ADC_AGND DIGITAL_VDDE3V3 VDD USB_HOST0_VDD2V5 USB_HOST0_VDD3V3 USB_HOST1_VDD2V5 USB_HOST1_VDD3V3 USB_DEVICE_VDD2V5 USB_DEVICE_VDD3V3 MCLK_VDD MCLK_VDD2V5 DITH_PLL_VDD_ANA DITH_VDD_2V5 DDR_VDDE1V8 ADC_AVDD RTC_VDD1V5 Doc ID 16755 Rev 4 SPEAr320 Ball Value N12 F10 F11 F12 G5 3.3 V J12 K12 L12 M12 F8 F9 G12 H5 H12 J5 L11 1 M11 L2 2 ...
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... SPEAr320 Table 4. Debug pin descriptions Group DEBUG Table 5. Serial memory interface (SMI) pin description Group SMI_DATAOUT SMI Table 6. USB pin descriptions Group Signal name USB_DEVICE_DP USB USB_DEVICE_DM DEV USB_DEVICE_VBUS Signal name Ball Direction TEST_0 K16 TEST_1 K15 TEST_2 K14 Input TEST_3 ...
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... Input 3.3 V tolerant, PD Over-current Reference Output resistor Analog Test Output Output Function ADC analog input channel ADC negative voltage reference ADC positive voltage reference SPEAr320 Pin type Bidirectional tolerant 4 mA Bidirectional tolerant 4 mA Analog Analog Pin type Analog buffer 2.5 V tolerant ...
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... SPEAr320 Table 8. DDR pin description Group Signal name DDR_MEM_ADD_0 DDR_MEM_ADD_1 DDR_MEM_ADD_2 DDR_MEM_ADD_3 DDR_MEM_ADD_4 DDR_MEM_ADD_5 DDR_MEM_ADD_6 DDR_MEM_ADD_7 DDR_MEM_ADD_8 DDR_MEM_ADD_9 DDR_MEM_ADD_10 DDR_MEM_ADD_11 DDR_MEM_ADD_12 DDR_MEM_ADD_13 DDR DDR_MEM_ADD_14 DDR_MEM_BA_0 DDR_MEM_BA_1 DDR_MEM_BA_2 DDR_MEM_RAS DDR_MEM_CAS DDR_MEM_WE DDR_MEM_CLKEN DDR_MEM_CLKP DDR_MEM_CLKN DDR_MEM_CS_0 DDR_MEM_CS_1 DDR_MEM_ODT_0 DDR_MEM_ODT_1 Ball Direction Function T2 T1 ...
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... R13 U15 I/O T15 T14 I/O R14 PEN_1 P10 Input R4 Power P4 Power J13 Input Doc ID 16755 Rev 4 SPEAr320 Function Pin type Data Lines SSTL_2/SSTL_1 8 (Lower byte) Differential Lower Data SSTL_2/SSTL_1 Strobe 8 Lower Data Mask Lower Gate Open SSTL_2/SSTL_1 8 Data Lines (Upper byte) ...
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... The 98 PL_GPIO and 4 PL_CLK pins have the following characteristics: – Output buffer: TTL 3.3 V capable – Input buffer: TTL, 3.3 V tolerant, selectable internal pull up/pull down (PU/PD) The PL_GPIOs can be configured in different modes. This allows SPEAr320 to be tailored for use in various applications like: – Metering concentrators – ...
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... Mbps) – 1 with hardware flow control (baud rate Mbps) – 1 with software flow control (baud rateup to 7 Mbps) ● SSP port ● 2 independent I2C interfaces ● PWM outputs ● GPIOs with interrupt capabilities 32/76 Doc ID 16755 Rev 4 SPEAr320 ...
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... I/O functions of the SPEAr320 IPs. To configure any PL_GPIO pin as GPIO, set the corresponding bit in the GPIO_Select(0 ..3) registers that are 102 bits write registers that select GPIO versus some IPs. Please refer to the SPEAr320 user manual for more detail about these registers. 4.3.6 Multiplexing scheme ...
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... EMI_A9 MII1_RXD0 EMI_A10 MII1_RXD1 EMI_A11 MII1_RXD2 EMI_A12 SPP_DATA0 MII1_RXD3 EMI_A13 SPP_DATA1 MII1_COL EMI_A14 SPP_DATA2 Doc ID 16755 Rev 4 SPEAr320 SMII automation networking MII automation networking Expanded automation Printer Programmer model control register bits (2:0) Alternate function Function in (enabled by GPIO embedded/ alternative 4 custom ...
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... SPEAr320 Table 10. PL_GPIO multiplexing scheme (continued) Configuration mode (enabled by Programmer model PL_GPIO_# / ball number 1 PL_GPIO_82/E15 CLD15 PL_GPIO_81/C17 CLD16 PL_GPIO_80/D16 CLD17 PL_GPIO_79/F14 CLD18 PL_GPIO_78/D15 CLD19 PL_GPIO_77/B17 CLD20 PL_GPIO_76/F13 CLD21 PL_GPIO_75/E14 CLD22 PL_GPIO_74/C16 CLD23 PL_GPIO_73/A17 CLAC PL_GPIO_72/B16 CLFP PL_GPIO_71/D14 CLLP PL_GPIO_70/C15 CLLE PL_GPIO_69/A16 ...
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... TMR_CLK3 SD_DAT1 TMR_CLK2 SD_DAT0 TMR_CLK1 0 UART0_DTR 0 UART0_RI 0 UART0_DSR 0 UART0_DCD 0 UART0_CTS 0 UART0_RTS SSP0_CS4 SSP0_CS3 SSP0_CS2 basGPIO5 basGPIO4 basGPIO3 SPEAr320 GPIO alternative mode GPIO_55 GPIO_54 GPIO_53 GPIO_52 GPIO_51 GPIO_50 GPIO_49 GPIO_48 GPIO_47 GPIO_46 GPIO_45 GPIO_44 GPIO_43 GPIO_42 GPIO_41 GPIO_40 GPIO_39 GPIO_38 GPIO_37 GPIO_36 ...
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... SPEAr320 Table 10. PL_GPIO multiplexing scheme (continued) Configuration mode (enabled by Programmer model PL_GPIO_# / ball number 1 PL_GPIO_30/B7 CAN1_RX PL_GPIO_29/A7 UART1_TX PL_GPIO_28/A6 UART1_RX PL_GPIO_27/B6 SMII0_TX PL_GPIO_26/A5 SMII0_RX PL_GPIO_25/C6 SMII1_TX PL_GPIO_24/B5 SMII1_RX PL_GPIO_23/A4 SMII_SYNC PL_GPIO_22/D6 SMII_CLKOUT PL_GPIO_21/C5 SMII_CLKIN PL_GPIO_20/B4 SSP1_MOSI PL_GPIO_19/A3 SSP1_CLK PL_GPIO_18/D5 SSP1_SS0 PL_GPIO_17/C4 ...
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... Standard Parallel port Note: For the full description of the I/O functions related to each IP, please refer to the corresponding sections of the SPEAR320 user manual. 4.4 PL_GPIO pin sharing for debug modes In some cases the PL_GPIO pins may be used in different ways for debugging purposes. ...
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... SPEAr320 1. Case 1 - All the PL_GPIO get values from Boundary scan registers during Ex-test instruction of JTAG . Typically this configuration is used to verify correctness of the soldering process during the production flow . 2. Case 2 - All the PL_GPIO maintain their original meaning but the JTAG Interface is connected to the processor. This configuration is useful during the development phase but offers only " ...
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... Original meaning BSR Value Original meaning BSR Value Original meaning BSR Value Original meaning BSR Value Original meaning BSR Value Original meaning BSR Value Original meaning Doc ID 16755 Rev 4 SPEAr320 Case 3 - full debug ARM_PIPESTATB[2] ARM_TRACE_PKTA[4] ARM_TRACE_PKTA[5] ARM_TRACE_PKTA[6] ARM_TRACE_PKTA[7] ARM_TRACE_PKTB[4] ARM_TRACE_PKTB[5] ARM_TRACE_PKTB[6] ARM_TRACE_PKTB[7] ...
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... SPEAr320 5 Memory map Table 13. SPEAr320 main memory map Start address 0x0000.0000 0x4000.0000 0xC000.0000 0xD000.0000 0xD008.0000 0xD010.0000 0xD018.0000 0xD020.0000 0xD080.0000 0xD100.0000 0xD180.0000 0xD280.0000 0xD800.0000 0xE080.0000 0xE100.0000 0xE110.0000 0xE120.0000 0xE130.0000 0xE180.0000 0xE190.0000 0xE1A0.0000 0xE210.0000 0xE220.0000 0xE280.0000 0xE290.0000 0xE800.0000 0xF000.0000 0xF010.0000 0xF110.0000 0xF120.0000 0xF800.0000 ...
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... Memory map Table 13. SPEAr320 main memory map (continued) Start address 0xFC00.0000 0xFC20.0000 0xFC40.0000 0xFC60.0000 0xFC80.0000 0xFC88.0000 0xFC90.0000 0xFC98.0000 0xFCA0.0000 0xFCA8.0000 0xFCB0.0000 0xFCB8.0000 0xFD00.0000 0xFF00.0000 Table 14. Reconfigurable array subsystem memory map Start address 0x4000_0000 0x4800_0000 0x4C00_0000 0x6000_0000 0x7000_0000 0x8000_0000 0x8000_4000 0x9000_0000 0xA000_0000 ...
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... SPEAr320 Table 14. Reconfigurable array subsystem memory map (continued) Start address 0xA9D0_0000 0xAA00_0000 0xAB00_0000 0xAC00_0000 0xB300_0000 End address Peripheral 0xA9FF_FFFF Reserved 0xAAFF_FFFF SMII0 0xABFF_FFFF SMII1/MII 0xB2FF_FFFF Reserved 0xBFFF_FFFF AHB interface Doc ID 16755 Rev 4 Memory map Description 43/76 ...
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... Supply voltage for the analog blocks (2) Supply voltage for the I/Os Maximum power consumption Doc ID 16755 Rev 4 Minimum value Maximum value - 0.3 1.44 - 0.3 3 0.3 2.16 -0.3 2.16 -55 150 -40 125 Max 420 160 (3) 930 SPEAr320 Unit °C °C Unit mA mA µ ...
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... SPEAr320 3. The maximum current and power values listed above, obtained with typical supply voltages, are not guaranteed to be the highest obtainable. These values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages ...
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... Min Max = 3V3 29 103 DDE Min Max -0.3 V -0.15 REF -0.3 V -0.125 REF V +0.15 V 2V5+0.3 REF DDE V +0.125 V 1V8+0.3 REF DDE 200 Min Typ 40.5 45 44.1 49 SPEAr320 Unit Unit V V Unit k k Unit Max Unit 49.5 53.9 ...
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... SPEAr320 Table 24. On die termination Symbol Termination value of resistance for on die RT1* Termination value of resistance for on die RT2* Table 25. Reference voltage Symbol V REFIN 6.7 Power up sequence It is recommended to power up the power supplies in the order shown in brought up first, followed by Figure 5. Power-up sequence V 1 ...
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... The MRESET must remain active for at least 10 ms after all the power supplies are in the correct range and should become active in no more than 10 µs when one of the power supplies goes out of the correct range. 48/76 Power-down sequence Doc ID 16755 Rev 4 SPEAr320 ...
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... SPEAr320 7 Timing requirements 7.1 DDR2 timing characteristics The characterization timing is done considering an output load all the DDR pads. The operating conditions are in worst case V=1. 40° 7.1.1 DDR2 read cycle timings Figure 7. DDR2 Read cycle waveforms DQS DQ Figure 8. DDR2 Read cycle path ...
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... DDR2 Write cycle timings Frequency 333 MHz 266 MHz 200 MHz 166 MHz 133 MHz 50/76 t4 max 2. max 1.36 1.55 1.86 2.11 2.49 Doc ID 16755 Rev 4 SPEAr320 t5 max t5 max 260 ps 260 ps 634 ps 634 max Unit -1.55 ns -1.36 ns -1. 794 ns -420 ...
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... SPEAr320 7.1.3 DDR2 command timings Figure 11. DDR2 Command waveforms CLK ADDRESS, STROBEs, AND CONTROL LINES Figure 12. DDR2 Command path Table 28. DDR2 Command timings Frequency 333 MHz 266 MHz 200 MHz 166 MHz 133 MHz 7.2 CLCD timing characteristics The characterization timing is done considering an output load all the outputs. ...
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... Tmax Tmin Tstable D SET Q Q CLR t3 Value ) 6 ns CLOCK ) 0. 0. -0.04 ns 3.62 ns 2.34 ns direct max - ( max min + [t direct max - (t max CLOCK Doc ID 16755 Rev 4 SPEAr320 Tf CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER t2 CLCP Frequency 166 MHz + t )]/2} = 4.7915 ns max min Tr the min ...
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... SPEAr320 7.2.2 CLCD timing characteristics divided clock Figure 15. CLCD waveform with CLCP divided CLCP CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER Figure 16. CLCD block diagram with CLCP divided t1 CLCDCLK Table 30. CLCD timings with CLCP divided Parameter t divided max CLOCK t divided max rise (t ...
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... Those values are referred to the common internal source clock which has a period of ns. HCLK 54/ signals Min 8.1067 SCLH 7.9874 SCLL 7.5274 SDAH 7.4081 SDAL Doc ID 16755 Rev 4 =125° worst case and A Set D Q Clr Q Set D Q Clr Q Max 11.8184 12.6269 11.2453 12.0530 SPEAr320 SCL SDA Unit ...
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... SPEAr320 Figure 19. Output signal waveforms for I The timing of high and low level of SCL (t Table 32. Time characteristics for I Table 33. Time characteristics for I Table 34. Time characteristics for signals SCLHigh high-speed mode Parameter t SU-STA t HD-STA t SU-DAT t HD-DAT t SU-STO t HD-STO fast speed mode Parameter t SU-STA ...
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... I C controller of SPEAr320 is one-clock cycle based (6 ns with the HCLK clock at 166 MHz). This time may be insufficient for some slave devices. A few slave devices may not receive the valid address due to the lack of SDA hold time and will not acknowledge even if the address is valid ...
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... SPEAr320 7.4.1 8-bit NAND Flash configuration Figure 21. Output pads for 8-bit NAND Flash configuration HCLK Figure 22. Input pads for 8-bit NAND Flash configuration .. ..2 2 Figure 23. Output command signal waveforms for 8-bit NAND Flash configuration NFCE NFCLE NFWE NFIO D SET CLR ... ...
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... TIO (h=1) Note: Values in Table 35 THCLK = 6 ns. 58/76 T ALE Address Data Out READ -> IO NFIO -> FFs Min -16.85 ns -16.84 ns 11.10 ns 11.18 ns 3.43 ns are referred to the common internal source clock which has a period of Doc ID 16755 Rev 4 SPEAr320 Max -19.38 ns -19.37 ns 13.04 ns 13.05 ns 8.86 ns ...
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... SPEAr320 7.4.2 16-bit NAND Flash configuration Figure 26. Output pads for 16-bit NAND Flash configuration HCLK Figure 27. Input pads for 16-bit NAND Flash configuration .. ..2 2 Figure 28. Output command signal waveforms 16-bit NAND Flash configuration NFCE NFCLE NFWE NFIO D SET Q Q CLR ... ...
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... The operating conditions are in worst case V=0.90 V T=125° C and in best case V=1. 40° C. 60/76 T ALE Address Data Out READ -> IO NFIO -> FFs MIN -16.85 ns -16.84 ns 11.10 ns 11.18 ns 3.27 ns are referred to the common internal source clock which has a period of Doc ID 16755 Rev 4 SPEAr320 MAX -19.38 ns -19.37 ns 13.04 ns 13.05 ns 11.35 ns ...
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... SPEAr320 7.5.1 MII transmit timing specifications Figure 31. MII TX waveforms MIITX_CLK Tmax Tmin MII_TXD0-MII_TXD3, MII_TXEN, MII_TXER Figure 32. Block diagram of MII TX pins MII_TX[0..3], MII_TXEN, MII_TXER CLK Table 37. MII TX timings Parameter max max min min min max t SETUP Note: To calculate the t you have to apply the following formula: t ...
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... Figure 33. MII RX waveforms MII_RXCLK MII_RXD0-MII_RXD3, MII_RXER, MII_RXDV Figure 34. Block diagram of MII RX pins MII_RX[0..3], MII_RXER, MII_RXDV MII_RXCLK 7.5.3 MDIO timing specifications Figure 35. MDC waveforms MDC Input MDIO Output 62/76 Tclock Tclock Tsetup Thold Tmax Tmi n Doc ID 16755 Rev 4 SPEAr320 SET Q Q CLR Tf Tr ...
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... SPEAr320 Figure 36. Paths from MDC/MDIO pads INPUT CLK Table 38. MDC/MDIO timing Parameter t period CLK t fall (t ) CLK f t rise (t ) CLK max CLK min CLK SETUPmax max HOLDmin min Note: When MDIO is used as output the data are launched on the falling edge of the clock as ...
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... Signal SMI_DATAIN Figure 38. SMI_DATAOUT/SMI_CSn data paths OUTPUT SMI_CLK 64/ SMI_CLK_i SMIDATAIN arrival Parameter t t d_max SMIDATAIN_arrival_max t t d_min SMIDATAIN_arrival_min t t cd_min SMI_CLK_i_arrival_min t t cd_max SMI_CLK_i_arrival_max t SETUP_max t t HOLD_min Doc ID 16755 Rev 4 SPEAr320 HCLK Value - t input_delay - t input_delay d_max cd_min - d_min cd_max HCLK HCLK ...
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... SPEAr320 Figure 39. SMI_DATAOUT timings SMI_CLK SMI_DATAOUT(FAST) SMI_DATAOUT(SLOW) Table 40. SMI_DATAOUT timings Signal SMI_DATAOUT Figure 40. SMICSn fall timings Table 41. SMI_CSn fall timings Signal SMI_CSn fall t t delay_min delay_max Parameter t t delay_max arrivalSMIDATAOUT_max t t delay_min arrivalSMIDATAOUT_min Parameter t t delay_max arrivalSMICSn_max_fall t t delay_min arrivalSMICSn_min_fall Doc ID 16755 Rev 4 ...
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... Input setup-hold/output delay Max Fall time 1.8209 Rise time 1.6320 Input setup time 8.27482 Input hold time -2.595889 2.039774 fall 1.922779 rise 1.69768 fall 1.7898169 rise 1.638069 Doc ID 16755 Rev 4 SPEAr320 Value - t arrival_SMI_CLK_min_fall - t arrival_SMI_CLK_max_fall Min 1.4092 1.1959 ...
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... SPEAr320 7.7 SSP timing characteristics This module provides a programmable length shift register which allows serial communication with other SSP devices through wire interface (SSP_CLK, SSP_MISO, SSP_MOSI and SSP_CSn). The SSP supports the following features: ● Master/Slave mode operations ● Chip-selects for interfacing to multiple slave SPI devices. ...
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... SSP_CLK (output) rising or falling edge Delay time, SSP_CLK (output) rising or falling edge to SSP_CSn (output) rising edge Doc ID 16755 Rev 4 Min Max. -0.411 -0.342 -0.411 -0.342 0.912 1.720 0.912 1.720 Min Max Clock -3.138 2.175 Clock -3.138 2.175 T/2 T SPEAr320 Unit Unit ...
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... SPEAr320 Figure 43. SPI master mode external timing (clock phase = 0) 7.7.2 SPI master mode timings (clock phase = 1) Table 47. Timing requirements for SPI master mode (clock phase = 1) No. t su(DIV- 4 CLKL) t su(DIV- 5 CLKH) t h(CLKL- 6 DIV) t h(CLKH- 7 DIV) Table 48. Switching characteristics over recommended operating conditions for SPI master mode (clock phase = ...
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... Figure 45. UART transmit and receive timings 70/76 Parameters Delay time, SSP_CSn (output) falling edge to first SSP_CLK (output) rising or falling edge Delay time, SSP_CLK (output) rising or falling edge to SSP_CSn (output) rising edge (Input) (Output) Doc ID 16755 Rev 4 SPEAr320 Min Max Unit T ns T/2 ns ...
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... SPEAr320 Table 49. UART transmit timing characteristics S.No Table 50. UART receive timing characteristics S.No where ( UART baud rate 7.9 ADC characteristics Table 51. 10-bit ADC characteristics Symbol Parameters f ADC_CLK frequency ADC_CLK AV ADC supply voltage DD V Positive reference voltage REFP V Negative reference voltage REFN ...
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... Doc ID 16755 Rev 4 SPEAr320 inches Min. Typ. Max. 0.0669 0.0106 0.0387 0.0078 0.0315 0.0177 0.0197 0.0217 0.5846 0.5906 0.5965 0.5039 0.5846 0.5906 0.5965 ...
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... SPEAr320 Figure 46. LFBGA289 package dimensions Table 53. Thermal resistance characteristics package LFBGA289 °C/W) JC 18.5 Doc ID 16755 Rev 4 Package information °C/W) JB 24.5 73/76 ...
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... Table 15: Absolute maximum ratings consumption. characteristics. Section 7.5: Ether MAC 10/100 Mbps timing interface. characteristics. and added saving. and Timing requirements Section 6.5: 3.3V I/O characteristics. characteristics. Section 2: Main features from > 6 Mbps into Mbps. SPEAr320 and Section 6.8: into and ...
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... SPEAr320 Table 54. Document revision history (continued) Date 02-Feb-2010 2 (continued) 18-Nov-2010 02-Dec-2010 Revision Changed the baud rate for the UARTs with Hardware flow control from “up to 460.8 Kbaud” into “ Mbps”. Table 14: Reconfigurable array subsystem memory typo error “UART23” into “UART2”. ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 76/76 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 16755 Rev 4 SPEAr320 ...