SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 18

• Manufacturer Part Number: SPEAR320-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR320-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr320
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 102
• Number Of Timers: 4
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10843

Architecture overview
3.15
3.16
18/76
GPIOs
A maximum of 102 GPIOs (PL_GPIOs) are available when part of the embedded or
customization IPs are not needed (see
Within its basic subsystem, SPEAr320 provides a base General Purpose Input/Output
(GPIO) block (basGPIO). The base GPIO block provides 6 programmable inputs or outputs.
Each input/output can be controlled in two distinct modes:
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Main features of the base GPIO block are:
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Other GPIO blocks are present in the reconfigurable array subsystem.
Parallel port
Main features:
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Software mode, through an APB interface.
Hardware mode, through a hardware control interface.
Six individually programmable input/output pins (default to input at reset)
An APB slave acting as control interface in "software mode"
Programmable interrupt generation capability on any number of pins.
Hardware control capability of GPIO lines for different system configurations.
Bit masking in both read and write operation through address lines.
Slave mode device interface for standard parallel port host
Supports unidirectional 8-bit data transfer from host to slave
Supports 9th bit for parity/data/command etc.
Maskable interrupts for data, device reset, auto line feed
APB input clock frequency required is 83 MHz for acknowledgement timings
Conforms to AMBA-APB specifications
Doc ID 16755 Rev 4
Section 4.3: Shared I/O pins
(PL_GPIOs)).
SPEAr320