SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 75

• Manufacturer Part Number: SPEAR320-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR320-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr320
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 102
• Number Of Timers: 4
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10843

SPEAr320
Table 54.
02-Dec-2010
02-Feb-2010
18-Nov-2010
Date
Document revision history (continued)
2 (continued)
Revision
3
4
Changed the baud rate for the UARTs with Hardware flow control
from “up to 460.8 Kbaud” into “up to 3 Mbps”.
Table 14: Reconfigurable array subsystem memory
typo error “UART23” into “UART2”.
Section 3.11: CAN
32 message RAM)” to “16 message objects (136 x 16 message
RAM)”.
Corrected a typo error in the
waveforms for 8-bit NAND Flash configuration
data signal waveforms for 16-bit NAND Flash
Updated
the end of the table.
Corrected the voltage capable of RTC in the
RTC, Reset and 3.3 V comparator pin
Updated figures of
Updated
MII TX
of MII RX pins
Corrected the speed of UART1 and UART2 in
UART1
Updated
pin
description
Minor text corrections.
Corrected pin assignment of UART0_RTS and CTS in
PL_GPIO multiplexing scheme
Added
Changed max. speed of UART2 and UART3 in feature descriptions
from 6 Mbps to 7 Mbps and updated
characteristics on page
Corrected SRAM size from 56K to 8 Kbytes in
features on page 9
Updated feature descriptions for the 3 UARTs in
UARTs on page 20
Doc ID 16755 Rev 4
descriptions,
pins,
Section 7.9: ADC characteristics on page 71
from “5 Mbps” into “6 Mbps”.
Table 3: Power supply pin description
Figure 31: MII TX
Table 2: Master clock, RTC, Reset and 3.3 V comparator
Figure 33: MII RX
Table 6: USB pin descriptions andTable 8: DDR pin
Section 7.4: FSMC timing
controller: changed “32 message objects (132 x
71.
waveforms,
Figure 25: In/out data address signal
Changes
waveforms,
Table 49: UART transmit timing
descriptions.
Figure 32: Block diagram of
Figure 34: Block diagram
Table 2: Master clock,
characteristics.
configuration.
Section 3.19.2:
and
Section 2: Main
and added a note at
Section 3.19:
Revision history
Figure 30: In/out
map: changed a
Table 10:
75/76