SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 21

• Manufacturer Part Number: SPEAR320-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR320-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr320
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 102
• Number Of Timers: 4
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10843

SPEAr320
3.21
Main features:
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Cryptographic co-processor (C3)
SPEAr320 has an embedded Channel Control Coprocessor (C3). C3 is a high-performance
instruction driven DMA based co-processor. It executes instruction flows generated by the
host processor. After it has been set-up by the host it runs in a completely autonomous way
(DMA data in, data processing, DMA data out), until the completion of all the requested
operations.
C3 has been used to accelerate the processing of cryptographic, security and network
security applications. It can be used for other types of data intensive applications as well.
Hardware cryptographic co-processor features are listed below:
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Compliance with the baseline JPEG standard (ISO/IEC 10918-1)
Single-clock per pixel encoding/decoding
Support for up to four channels of component color
8-bit/channel pixel depths
Programmable quantization tables (up to four)
Programmable Huffman tables (two AC and two DC)
Programmable minimum coded unit (MCU)
Configurable JPEG header processing
Support for restart marker insertion
Use of two DMA channels and of two 8 x 32-bits FIFO's (local to the JPEG) for efficient
transferring and buffering of encoded/decoded data from/to the CODEC core.
Supported cryptographic algorithms:
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Instruction driven DMA based programmable engine.
AHB master port for data access from/to system memory.
AHB slave port for co-processor register accesses and initial engine-setup.
The co-processor is fully autonomous (DMA input reading, cryptographic operation
execution, DMA output writing) after being set up by the host processor.
The co-processor executes programs written by the host in memory, it can execute an
unlimited list of programs.
The co-processor supports hardware chaining of cryptographic blocks for optimized
execution of data-flow requiring multiple algorithms processing over the same set of
data (for example encryption + hashing on the fly).
Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes.
Data encryption standard (DES) cipher in ECB and CBC modes.
SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests.
Doc ID 16755 Rev 4
Architecture overview
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