SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 15

• Manufacturer Part Number: SPEAR320-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR320-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr320
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 102
• Number Of Timers: 4
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10843

SPEAr320
3.10
Figure 3.
Each Ethernet port provides the following features:
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MII Ethernet controller
SPEAr320 provides an Ethernet MAC 10/100 Universal (commonly referred to as MAC-
UNIV), enabling to transmit and receive data over Ethernet in compliance with the IEEE
802.3-2002 standard.
Compatible with IEEE Standard 802.3
10 and 100 Mbit/s operation
Full and half duplex operation
Statistics counter registers for RMON/MIB
Interrupt generation to signal receive and transmit completion
Automatic pad and CRC generation on transmitted frames
Automatic discard of frames received with errors
Address checking logic supports up to four specific 48-bit addresses
Supports promiscuous mode where all valid received frames are copied to memory
Hash matching of unicast and multicast destination addresses
External address matching of received frames
Physical layer management through MDIO interface
Supports serial network interface operation
Half duplex flow control by forcing collisions on incoming frames
Full duplex flow control with recognition of incoming pause frames and hardware
generation of transmitted pause frames
Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority
tagged frames
Multiple buffers per receive and transmit frame
Wake on LAN support
Jumbo frames of up to 10240 bytes supported
Configurable Endianess for the DMA Interface (AHB Master)
Typical SMII system
2 MAC
ports
Doc ID 16755 Rev 4
SYNC
2 Rx
2 Tx
Clock
2x PHY
Architecture overview
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