SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 17

• Manufacturer Part Number: SPEAR320-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR320-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr320
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 102
• Number Of Timers: 4
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10843

SPEAr320
3.13
3.14
Both hosts can manage an external power switch, providing a control line to enable or
disable the power, and an input line to sense any over-current condition detected by the
external switch.
One host controller at time can perform high speed transfer.
USB2 device controller
Main features:
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CLCD controller
SPEAr320 has a color liquid crystal display controller (CLCDC) that provides all the
necessary control signals to interface directly to a variety of color and monochrome LCD
panels.
Main features:
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Supports the 480 Mbps high-speed mode (HS) for USB 2.0, as well as the 12 Mbps
full-speed (FS) and the low-speed (LS modes) for USB 1.1
Supports 16 physical endpoints, configurable as different logical endpoints
Integrated USB transceiver (PHY)
Local 4 Kbyte FIFO shared among all the endpoints
DMA mode and slave-only mode are supported
In DMA mode, the UDC supports descriptor-based memory structures in application
memory
In both modes, an AHB slave is provided by UDC-AHB, acting as programming
interface to access to memory-mapped control and status registers (CSRs)
An AHB master for data transfer to system memory is provided, supporting 8, 16, and
32-bit wide data transactions on the AHB bus
A USB plug (UPD) detects the connection of a cable.
Resolution programmable up to 1024 x 768
16-bpp true-color non-palletized, for color STN and TFT
24-bpp true-color non-palletized, for color TFT
Supports single and dual panel mono super twisted nematic (STN) displays with 4 or 8-
bit interfaces
Supports single and dual-panel color and monochrome STN displays
Supports thin film transistor (TFT) color displays
15 gray-level mono, 3375 color STN, and 32 K color TFT support
1, 2, or 4 bits per pixel (bpp) palletized displays for mono STN
1, 2, 4 or 8-bpp palletized color displays for color STN and TFT
Programmable timing for different display panels
256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM physically frame, line
and pixel clock signals
AC bias signal for STN and data enable signal for TFT panels patented gray scale
algorithm
Supports little and big-endian
Doc ID 16755 Rev 4
Architecture overview
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