AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 608

• Manufacturer Part Number: AT91SAM7SE256B-AUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-AUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

39.6.3
Name:
Access:
• CHx: Channel x Enable
0 = No effect.
1 = Enables the corresponding channel.
39.6.4
Name:
Access:
• CHx: Channel x Disable
0 = No effect.
1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver-
sion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
608
CH7
CH7
31
23
15
31
23
15
–
–
–
7
–
–
–
7
SAM7SE512/256/32 Preliminary
ADC Channel Enable Register
ADC Channel Disable Register
CH6
CH6
30
22
14
30
22
14
ADC_CHER
Write-only
–
–
–
6
ADC_CHDR
Write-only
–
–
–
6
CH5
CH5
29
21
13
29
21
13
–
–
–
5
–
–
–
5
CH4
CH4
28
20
12
28
20
12
–
–
–
4
–
–
–
4
CH3
CH3
27
19
11
27
19
11
–
–
–
–
–
–
3
3
CH2
CH2
26
18
10
26
18
10
–
–
–
2
–
–
–
2
CH1
CH1
25
17
25
17
–
–
–
–
–
–
9
1
9
1
6222F–ATARM–14-Jan-11
CH0
CH0
24
16
24
16
–
–
8
–
0
–
–
8
–
0