AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 133

• Manufacturer Part Number: AT91SAM7SE256B-AUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-AUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.3.4.6
20.3.4.7
20.3.4.8
6222F–ATARM–14-Jan-11
Flash Security Bit Command
SAM7SE512 Select EFC Command
Memory Write Command
GP NVM bits can be read using Get Fuse Bit command (GFB). When a bit set in the Bit Mask is
returned, then the corresponding fuse bit is set.
Table 20-25. Get General-purpose NVM Bit Command
Security bits can be set using Set Security Bit command (SSE). Once the security bit is active,
the Fast Flash programming is disabled. No other command can be run. Only an event on the
Erase pin can erase the security bit once the contents of the Flash have been erased.
The SAM7SE512 security bit is controlled by the EFC0. To use the Set Security Bit command,
the EFC0 must be selected using the Select EFC command.
Table 20-26. Set Security Bit Command
The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default
EFC controller is EFC0. The Select EFC command (SEFC) allows selection of the current EFC
controller.
Table 20-27. Select EFC Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. An internal address
buffer is automatically increased.
Table 20-28. Write Command
Read/Write
Write
Read
Read/Write
Write
Step
1
2
Read/Write
Write
Write
Write
Write
Write
Write
Handshake Sequence
Write handshaking
Write handshaking
DR Data
GFB
Bit Mask
DR Data
SSE
DR Data
(Number of Words to Write) << 16 | (WRAM)
Address
Memory [address]
Memory [address+4]
Memory [address+8]
Memory [address+(Number of Words to Write - 1)* 4]
SAM7SE512/256/32 Preliminary
MODE[3:0]
CMDE
DATA
DATA[15:0]
SEFC
0 = Select EFC0
1 = Select EFC1
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