AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 554

IC ARM7 MCU FLASH 256K 128-LQFP

AT91SAM7SE256B-AUR

Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM7SE256B-AUR

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7SE256B-AUR
Manufacturer:
Atmel
Quantity:
10 000
37.6.12
Name:
Access:
• CNT: Channel Counter Register
Internal counter value. This register is reset when:
the channel is enabled (writing CHIDx in the PWM_ENA register).
the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
37.6.13
Name:
Access:
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modify-
ing the waveform period or duty-cycle.
Only the first 16 bits (internal channel counter size) are significant.
554
CPD (PWM_CMRx Register)
31
23
15
31
23
15
7
7
SAM7SE512/256/32 Preliminary
PWM Channel Counter Register
PWM Channel Update Register
0
1
30
22
14
30
22
14
6
6
PWM_CCNTx
Read-only
PWM_CUPDx
Write-only
The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the
beginning of the next period.
The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning
of the next period.
29
21
13
29
21
13
5
5
28
20
12
28
20
12
4
4
CUPD
CUPD
CUPD
CUPD
CNT
CNT
CNT
CNT
27
19
11
27
19
11
3
3
26
18
10
26
18
10
2
2
25
17
25
17
9
1
9
1
6222F–ATARM–14-Jan-11
24
16
24
16
8
0
8
0

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