AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 196

• Manufacturer Part Number: AT91SAM7SE256B-AUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-AUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.7.1
Name:
Access:
Reset Value:
• NWS: Number of Wait States
This field defines the Read and Write signal pulse length from 1 cycle up to 128 cycles.
Note:
Note:
• WSEN: Wait State Enable
0: Wait states are disabled.
1: Wait states are enabled.
• TDF: Data Float Time
The external bus is marked occupied and cannot be used by another chip select during TDF cycles. Up to 15 cycles can be
defined and represents the time allowed for the data output to go to high impedance after the memory is disabled.
• BAT: Byte Access Type
This field is used only if DBW defines a 16-bit data bus.
0: Chip select line is connected to two 8-bit wide devices.
1: Chip select line is connected to a 16-bit wide device.
196
Number of Wait States
WSEN
DRP
31
23
15
–
–
7
When WSEN is 0, NWS will be read to 0 whichever the previous programmed value should be.
1. Assuming WSEN Field = 0.
X + 1
SAM7SE512/256/32 Preliminary
SMC Chip Select Registers
0
1
2
(1)
30
22
14
SMC_CSR0..SMC_CSR7
Read/Write
See
–
6
Table 22-4 on page 195
DBW
Up to X = 127
NWS Field
Don’t Care
RWHOLD
0
1
29
21
13
–
5
Standard Read Protocol
BAT
NRD Pulse Length
28
20
12
–
4
X + 1+ ½ cycles
1 + ½ cycles
2 + ½ cycles
½ cycle
NWS
27
19
11
–
–
3
Early Read Protocol
NRD Pulse Length
X + 2 cycles
2 cycles
3 cycles
1 cycle
26
18
10
–
2
TDF
RWSETUP
25
17
9
1
NWR Pulse Length
6222F–ATARM–14-Jan-11
ACSS
X + 1 cycle
2 cycles
½ cycle
1 cycle
24
16
8
0