AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 126
AT91SAM7SE256B-AUR
Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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20.2.5.6
20.2.5.7
20.2.5.8
126
SAM7SE512/256/32 Preliminary
Flash Security Bit Command
SAM7SE512 Select EFC Command
Memory Write Command
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is
active, the Fast Flash programming is disabled. No other command can be run. An event on the
Erase pin can erase the security bit once the contents of the Flash have been erased.
The SAM7SE512 security bit is controlled by the EFC0. To use the Set Security Bit command,
the EFC0 must be selected using the Select EFC command.
Table 20-13. Set Security Bit Command
The commands WPx, EA, xLB, xFB are executed using the current EFC controller. The default
EFC controller is EFC0. The Select EFC command (SEFC) allows selection of the current EFC
controller.
Table 20-14. Select EFC Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking
can be chained; an internal address buffer is automatically increased.
Table 20-15. Write Command
Step
1
2
Step
1
2
Step
1
2
3
4
5
6
7
...
n
n+1
n+2
n+3
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
...
Write handshaking
Write handshaking
Write handshaking
Write handshaking
MODE[3:0]
CMDE
ADDR0
ADDR1
ADDR2
ADDR3
DATA
DATA
...
ADDR0
ADDR1
ADDR2
ADDR3
MODE[3:0]
CMDE
DATA
MODE[3:0]
CMDE
DATA
DATA[15:0]
WRAM
32-bit Memory Address First byte
32-bit Flash Address
32-bit Flash Address
32-bit Flash Address Last Byte
*Memory Address++
*Memory Address++
...
32-bit Memory Address First byte
32-bit Flash Address
32-bit Flash Address
32-bit Flash Address Last Byte
DATA[15:0]
SSE
0
DATA[15:0]
SEFC
0 = Select EFC0
1 = Select EFC1
6222F–ATARM–14-Jan-11
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