DR-TRC104-2400-DK RFM, DR-TRC104-2400-DK Datasheet - Page 21

KIT DEV FOR TRC104

DR-TRC104-2400-DK

Manufacturer Part Number
DR-TRC104-2400-DK
Description
KIT DEV FOR TRC104
Manufacturer
RFM
Type
Transceiverr

Specifications of DR-TRC104-2400-DK

Frequency
2.4GHz
For Use With/related Products
TRC104
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
583-1137
Figure 20 and Table 5 show the timing for a configuration write sequence to the TRC104.
7.2 Transmit/Receive FIFO Access
Serial data is sent or received through the FIFO according to the TRC104 mode of operation. If the TRC104 is
configured for Burst Receive Mode, a FIFO read transaction is implemented on the serial interface. If the TRC104
is configured for Burst Transmit Mode, a FIFO write transaction is implemented on the serial interface. The CS pin
must be held low during FIFO transactions. If the CS is allowed to go high, the TRC104 will interpret the data as a
register configuration transaction and possibly corrupt the device configuration. See Sections 5.2.1 and 5.2.2 for
details on Burst Transmit Mode and Burst Receive Mode using the FIFO.
8 Configuration Registers
The TRC104’s user configuration registers are mapped in the address range of 0x00 through 0x18. Sections 8.1
through 8.17 below provide the details for each configuration register. Power-up default settings for the
configuration register bit and byte patterns are shown in bold.
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Item
T1
T2
T3
T4
T5
T6
Item
T1
T2
T3
T4
T5
Description
CS to 1
SCLK Cycle Time
Setup Time
Hold Time
Data Bit Hold Time
Last Bit to CS Time
Description
CS to 1
SCLK cycle time
Setup time
Hold time
Last bit to CS time
Technical support +1.800.704.6079
st
st
Bit Time
bit time
Figure 20
Table 14
Table 15
Min
200
Min
200
20
10
10
50
20
10
10
50
Typ
Typ
Max
Max
20
Unit
µs
ns
ns
ns
ns
Unit
µs
ns
ns
ns
ns
ns
TRC104 - 08/13/09
Page 21 of 33

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