MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 89

• Manufacturer Part Number: MC711P2CFNE3
• Description: IC MCU 8BIT 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711P2CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4 Transmit operation
5.5 Receive operation
MC68HC11P2 — Rev 1.0
Selection of the word length is controlled by the M bit of SCCR1.
The SCI transmitter includes a parallel data register (SCDRH/SCDRL)
and a serial shift register. The contents of the shift register can only be
written through the serial data registers. This double buffered operation
allows a character to be shifted out serially while another character is
waiting in the serial data registers to be transferred into the shift register.
The output of the shift register is applied to TXD as long as transmission
is in progress or the transmit enable (TE) bit of serial communication
control register 2 (SCCR2) is set. The block diagram,
the transmit serial shift register and the buffer logic at the top of the
figure.
During receive operations, the transmit sequence is reversed. The serial
shift register receives data and transfers it to the parallel receive data
registers (SCDRH/SCDRL) as a complete word. This double buffered
operation allows a character to be shifted in serially while another
character is still in the serial data registers. An advanced data recovery
scheme distinguishes valid data from noise in the serial data stream.
The data input is selectively sampled to detect receive data, and majority
sampling logic determines the value and integrity of each bit.
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A stop bit, logic one, used to indicate the end of a frame. (A frame
consists of a start bit, a character of eight or nine data bits, and a
stop bit.)
A break (defined as the transmission or reception of a logic zero
for some multiple number of frames).
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
Figure
Transmit operation
Technical Data
5-2, shows