MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 144

• Manufacturer Part Number: MC711P2CFNE3
• Description: IC MCU 8BIT 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711P2CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer input capture 1 (TIC1) high $0010 (bit 15) (14)
Timer input capture 2 (TIC2) high $0012 (bit 15) (14)
Timer input capture 3 (TIC3) high $0014 (bit 15) (14)
Timing System
8.4.2 TIC1–TIC3 — Timer input capture registers
Technical Data
Timer input capture 1 (TIC1) low $0011 (bit 7)
Timer input capture 2 (TIC2) low $0013 (bit 7)
Timer input capture 3 (TIC3) low $0015 (bit 7)
When an edge has been detected and synchronized, the 16-bit free-
running counter value is transferred into the input capture register pair
as a single 16-bit parallel transfer. Timer counter value captures and
timer counter incrementing occur on opposite half-cycles of the phase 2
clock so that the count value is stable whenever a capture occurs. Input
capture values can be read from a pair of 8-bit read-only registers. A
read of the high-order byte of an input capture register pair inhibits a new
capture transfer for one bus cycle. If a double-byte read instruction, such
as LDD, is used to read the captured value, coherency is assured. When
a new input capture occurs immediately after a high-order byte read,
transfer is delayed for an additional cycle but the value is not lost.
The TICx registers are not affected by reset.
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Address bit 7
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Timing System
bit 6
(6)
(6)
(6)
bit 5
(13)
(13)
(13)
(5)
(5)
(5)
bit 4
(12)
(12)
(12)
(4)
(4)
(4)
bit 3
(11)
(11)
(11)
(3)
(3)
(3)
bit 2
(10)
(10)
(10)
(2)
(2)
(2)
MC68HC11P2 — Rev 1.0
bit 1
(9)
(9)
(9)
(1)
(1)
(1)
(bit 8)
(bit 0)
(bit 8)
(bit 0)
(bit 8)
(bit 0)
bit 0
on reset
affected
affected
affected
affected
affected
affected
State
not
not
not
not
not
not