MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 135

• Manufacturer Part Number: MC711P2CFNE3
• Description: IC MCU 8BIT 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711P2CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.7.3 SPDR — SPI data register
7.7.4 OPT2 — System configuration options register 2
MC68HC11P2 — Rev 1.0
System config. options 2 (OPT2) $0038 LIRDV CWOM
SPI data (SPDR)
The SPDR is used when transmitting or receiving data on the serial bus.
Only a write to this register initiates transmission or reception of a byte,
and this only occurs in the master device. At the completion of
transferring a byte of data, the SPIF status bit is set in both the master
and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun
and the loss of the byte that caused the overrun, the first SPIF must be
cleared by the time a second transfer of data from the shift register to the
read buffer is initiated.
SPI is double buffered in and single buffered out.
LIRDV — LIR driven (refer to
CWOM — Port C wired-OR mode (refer to
STRCH — Stretch external accesses (refer to
On-Chip
Freescale Semiconductor, Inc.
Address bit 7
Address bit 7
For More Information On This Product,
$002A (bit 7)
1 = Enable LIR drive high pulse.
0 = LIR only driven low – requires pull-up on pin.
1 = Port C outputs are open-drain.
0 = Port C operates normally.
1 = Off-chip accesses are extended by one E clock cycle.
0 = Normal operation.
Memory)
Serial Peripheral Interface (SPI)
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bit 6
bit 6
(6)
STRC
bit 5
bit 5
(5)
H
Operating Modes and On-Chip
IRVNE LSBF SPR2
bit 4
bit 4
(4)
bit 3
bit 3
(3)
Parallel
Serial Peripheral Interface (SPI)
bit 2
bit 2
(2)
Operating Modes and
bit 1
bit 1
Input/Output)
(1)
0
(bit 0)
bit 0
bit 0
0
Technical Data
SPI registers
Memory)
000x 0000
on reset
on reset
affected
State
State
not