MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 191

• Manufacturer Part Number: MC711P2CFNE3
• Description: IC MCU 8BIT 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711P2CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC11P2 — Rev 1.0
These bits can be read at any time. The value read is the one latched
into the register from the EEPROM cells during the last reset sequence.
A new value programmed into this register is not readable until after a
subsequent reset sequence. Unused bits always read as ones.
If SMOD = 1, CONFIG bits can be written at any time. If SMOD = 0,
CONFIG bits can only be written using the EEPROM programming
sequence, and are neither readable nor active until latched via the next
reset.
ROMAD — ROM mapping control (refer to
Chip
Bits [6,5] — Not implemented; always read one
PAREN — Pull-up assignment register enable (refer to
Input/Output)
NOSEC — EEPROM security disabled (refer to
On-Chip
NOCOP — COP system disable
ROMON — ROM enable (refer to
Memory)
EEON — EEPROM enable (refer to
Memory)
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1 = ROM addressed from $8000 to $FFFF.
0 = ROM addressed from $0000 to $7FFF (expanded mode only).
1 = PPAR register enabled; pull-ups can be enabled using PPAR.
0 = PPAR register disabled; all pull-ups disabled.
1 = Disable security.
0 = Enable security.
1 = COP system disabled.
0 = COP system enabled (forces reset on timeout).
1 = ROM included in the memory map.
0 = ROM excluded from the memory map.
1 = EEPROM included in the memory map.
Memory)
Memory)
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Resets and Interrupts
Operating Modes and On-Chip
Operating Modes and On-Chip
Operating Modes and On-
Operating Modes and
Resets and Interrupts
Parallel
Technical Data
Resets