MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 36

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MC711P2CFNE3

Manufacturer Part Number
MC711P2CFNE3
Description
IC MCU 8BIT 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC711P2CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
MI Bus, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC711P2CFNE3
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Pin Descriptions
2.13.2 Port B
2.13.3 Port C
Technical Data
outputs. Writes to PORTA do not change the pin state when the pins are
configured for timer output compares.
Out of reset, port A pins [7:0] are general-purpose high-impedance
inputs. When the functions associated with these pins are disabled, the
bits in DDRA govern the I/O state of the associated pin. For further
information, refer to
Port B is an 8-bit general-purpose I/O port with a data register (PORTB)
and a data direction register (DDRB). In single chip mode, port B pins are
general-purpose I/O pins (PB[7:0]). In expanded mode, port B pins act
as the high-order address lines (A[15:8]) of the address bus.
PORTB can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTB is written, the data is stored in
internal latches. The pins are driven only if they are configured as
outputs in single chip or bootstrap mode. For further information, refer to
Parallel
Port B pins include on-chip pull-up devices which can be enabled or
disabled.
Port C is an 8-bit general-purpose I/O port with a data register (PORTC)
and a data direction register (DDRC). In single chip mode, port C pins
are general-purpose I/O pins (PC[7:0]). In the expanded mode, port C
pins are configured as data bus pins (D[7:0]).
PORTC can be read at any time: inputs return the pin level; outputs
return the pin driver input level. If PORTC is written, the data is stored in
internal latches. The pins are driven only if they are configured as
outputs in single chip or bootstrap mode. Port C pins are general-
purpose inputs out of reset in single chip and bootstrap modes. In
expanded and test modes, these pins are data bus lines out of reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
Input/Output.
Go to: www.freescale.com
Pin Descriptions
Parallel
Input/Output.
MC68HC11P2 — Rev 1.0

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