MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 121

• Manufacturer Part Number: MC711P2CFNE3
• Description: IC MCU 8BIT 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711P2CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC11P2 — Rev 1.0
RDRF2 — Receive data register full flag 2
OR2 — Bit error 2
NF2 — Noise error flag 2
This bit is set when noise is detected on the receive line during an
MI BUS pull field.
1. Note that TDREx and TCx will both behave in the same way as during normal SCI transmis-
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This bit is set when the contents of the receiver serial shift register
have been transferred to the receiver data register.
The EOF (end-of-frame) during an MI BUS pull-field is a continuous
square wave, which will result in multiple RDRFs. This may be dealt
with in any of the following ways:
This bit is set when a push field bit value on the MI BUS does not
match the bit value that was sent. This is known as an MI BUS bit
error. OR2 does not generate an interrupt request in MI BUS mode.
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1 = Contents of the receiver serial shift register have been
0 = Contents of the receiver serial shift register have not been
1 = A bit error has been detected.
0 = No bit error has been detected.
1 = Noise detected.
0 = No noise detected.
– By clearing the RIE2 mask, ignoring unneeded RDRF2s,
– By clearing the RE2 bit when a pull field is complete, followed
– By disabling the MI BUS.
Motorola Interconnect Bus (MI BUS)
transferred to the receiver data register.
transferred to the receiver data register.
initiating a push field, waiting for TDRE2
the RDRF2;
by setting the RE2 bit after the TDRE2
the next push field is asserted;
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Motorola Interconnect Bus (MI BUS)
†
(1)
flag associated with
SCI/MI BUS2 registers
and then clearing
Technical Data