MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 261

• Manufacturer Part Number: MC711P2CFNE3
• Description: IC MCU 8BIT 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711P2CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

object code — The output from an assembler or compiler that is itself executable machine code,
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
operand — Data on which an operation is performed. Usually a statement consists of an
oscillator — A circuit that produces a constant frequency square wave that is used by the
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a pointer register because its
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
MC68HC11P2 — Rev 1.0
or is suitable for processing to produce executable machine code.
connected to the power supply to provide the logic 1 output voltage.
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
computer as a timing and sequencing reference.
cannot be reprogrammed.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
synchronized to a reference signal.
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
voltage levels, V
DD
and V
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Glossary
Technical Data
Glossary