MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 130

• Manufacturer Part Number: MC711P2CFNE3
• Description: IC MCU 8BIT 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711P2CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
7.5.4 Slave select
7.6 SPI system errors
Technical Data
master device, select the clock rate. In a slave device, SPR[1:0] have no
effect on the operation of the SPI.
The slave select SS input of a slave device must be externally asserted
before a master device can exchange data with the slave device. SS
must be low before data transactions begin and must stay low for the
duration of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault
error flag (MODF) is set in the serial peripheral status register (SPSR).
To disable the mode fault circuit, write a one in bit 5 of the port D data
direction register. This sets the SS pin to act as a general-purpose
output, rather than a dedicated input to the slave select circuit, thus
inhibiting the mode fault flag. The other three lines are dedicated to the
SPI whenever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS.
CPHA settings should be identical for master and slave. When CPHA =
0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS
must go high between successive characters in an SPI message. When
CPHA = 1, SS can be left low between successive SPI characters. In
cases where there is only one SPI slave MCU, its SS line can be tied to
V
Two kinds of system errors can be detected by the SPI system. The first
type of error arises in a multiple-master system when more than one SPI
device simultaneously tries to be a master. This error is called a mode
fault. The second type of error, write collision, indicates that an attempt
was made to write data to the SPDR while a transfer was in progress.
When the SPI system is configured as a master and the SS input line
goes to active low, a mode fault error has occurred — usually because
SS
Freescale Semiconductor, Inc.
as long as only CPHA = 1 clock mode is used.
For More Information On This Product,
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
MC68HC11P2 — Rev 1.0