MC711P2CFNE3 Freescale Semiconductor, MC711P2CFNE3 Datasheet - Page 150

• Manufacturer Part Number: MC711P2CFNE3
• Description: IC MCU 8BIT 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC711P2CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing System
8.5.6 TCTL1 — Timer control register 1
8.5.7 TMSK1 — Timer interrupt mask register 1
Technical Data
Timer interrupt mask 1 (TMSK1) $0022
Timer control 1 (TCTL1)
NOTE:
The bits of this register specify the action taken as a result of a
successful OCx compare.
OM[2:5] — Output mode
OL[2:5] — Output level
Use this 8-bit register to enable or inhibit the timer input capture and
output compare interrupts.
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in
TMSK1 enable the corresponding interrupt sources.
OC1I–OC4I — Output compare x interrupt enable
Freescale Semiconductor, Inc.
These control bit pairs are encoded to specify the action taken after a
successful OCx compare. OC5 functions only if the I4/O5 bit in the
PACTL register is clear.
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware
interrupt sequence is requested.
Address bit 7
Address bit 7
For More Information On This Product,
$0020
1 = OCx interrupt is enabled.
0 = OCx interrupt is disabled.
OMx
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OC1I OC2I OC3I OC4I I4/O5I
OM2
0
0
1
1
Timing System
bit 6
OL2
bit 6
OLx
0
1
0
1
OM3
bit 5
bit 5
Timer disconnected from OCx pin logic
Toggle OCx output line
Clear OCx output line to 0
Set OCx output line to 1
Action taken on successful compare
bit 4
OL3
bit 4
OM4
bit 3
bit 3
bit 2
OL4
bit 2
IC1I
MC68HC11P2 — Rev 1.0
OM5
bit 1
bit 1
IC2I
OL5 0000 0000
bit 0
bit 0
IC3I 0000 0000
on reset
on reset
State
State