HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 756
HD64F2134FA20
Manufacturer Part Number
HD64F2134FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2134FA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 24 Power-Down State
24.9
24.9.1
If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0,
the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, the CPU
makes a transition to subsleep mode.
In this mode, the CPU and all on-chip supporting modules except TMR0, TMR1, WDT0, and
WDT1 stop. As long as the prescribed voltage is supplied, the contents of some of the CPU’s
internal registers and on-chip RAM are retained, and I/O ports retain their states prior to the
transition.
24.9.2
Subsleep mode is cleared by an interrupt (on-chip supporting module interrupt, NMI pin, or pin
IRQ0 to IRQ7), or by means of the RES pin or STBY pin.
Clearing with an Interrupt: When an interrupt request signal is input, subsleep mode is cleared
and interrupt exception handling is started. Subsleep mode cannot be cleared with an IRQ0 to
IRQ7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting
module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable
register or masked by the CPU.
Clearing with the RES
Software Standby Mode.
Clearing with the STBY
standby mode
Rev. 4.00 Jun 06, 2006 page 700 of 1004
REJ09B0301-0400
Subsleep Mode
Clearing Subsleep Mode
Subsleep Mode
RES Pin: See “Clearing with the RES Pin” in section 24.6.2, Clearing
RES
RES
STBY
STBY
STBY Pin: When the STBY pin is driven low, a transition is made to hardware
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