HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 122

• Manufacturer Part Number: HD64F2134FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2134FA20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 2 CPU
stop mode permits halting of the operation of individual modules, other than the CPU. Subactive
mode, subsleep mode, and watch mode are power-down modes that use subclock input. For
details, refer to section 24, Power-Down State.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
software standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the
low-power control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop
immediately after execution of the SLEEP instruction. The contents of CPU registers are retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR
and the PSS bit in the WDT1 timer control/status register (TCSR) are both cleared to 0. In
software standby mode, the CPU and clock halt and all MCU operations stop. As long as a
specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The
I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin
goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The
on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM
contents are retained.
2.9
2.9.1
The CPU is driven by a system clock, denoted by the symbol . The period from one rising edge
of to the next is referred to as a “state.” The memory cycle or bus cycle consists of one, two, or
three states. Different methods are used to access on-chip memory, on-chip supporting modules,
and the external address space.
2.9.2
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows
the pin states.
Rev. 4.00 Jun 06, 2006 page 66 of 1004
REJ09B0301-0400
Overview
On-Chip Memory (ROM, RAM)
Basic Timing