HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 130

• Manufacturer Part Number: HD64F2134FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2134FA20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 3 MCU Operating Modes
Bit 6—IOS Enable (IOSE): Controls the function of the AS/IOS pin in expanded mode.
Bit 6
IOSE
0
1
Note:
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a
read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow.
Bit 3
XRST
0
1
Bit 1—Host Interface Enable (HIE): This bit controls CPU access to the host interface data
registers and control registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2), the
keyboard controller and MOS input pull-up control registers (KMIMR and KMPCR), the 8-bit
timer (channel X and Y) data registers and control registers (TCRX/TCRY, TCSRX/TCSRY,
TICRR/TCORAY, TICRF/TCORBY, TCNTX/TCNTY, TCORC/TISR, TCORAX, and
TCORBX), and the timer connection control registers (TCONRI, TCONRO, TCONRS, and
SEDGR).
Bit 1
HIE
0
1
Rev. 4.00 Jun 06, 2006 page 74 of 1004
REJ09B0301-0400
* In the H8S/2138 F-ZTAT A-mask version, the address range is from H'(FF)F000 to
H'(FF)F7FF.
Description
The AS/IOS pin functions as the address strobe pin (AS)
(Low output when accessing an external area)
The AS/IOS pin functions as the I/O strobe pin (IOS)
(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F) *
Description
A reset is generated by watchdog timer overflow
A reset is generated by an external reset
Description
In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to 8-
bit timer (channel X and Y) data registers and control registers, and timer connection
control registers, is permitted
In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to
host interface data registers and control registers, and keyboard controller and MOS
input pull-up control registers, is permitted
(Initial value)
(Initial value)
(Initial value)