HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 171

• Manufacturer Part Number: HD64F2134FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2134FA20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Interrupts KIN7 to KIN0: Interrupts KIN7 to KIN0 are requested by input signals at pins KIN7
to KIN0. When any of pins KIN7 to KIN0 are used as key-sense inputs, the corresponding
KMIMR bits should be cleared to 0 to enable those key-sense input interrupts. The remaining
unused key-sense input KMIMR bits should be set to 1 to disable those interrupts. Interrupts KIN7
to KIN0 correspond to the IRQ6 interrupt. Interrupt request generation pin conditions, interrupt
request enabling, interrupt control level setting, and interrupt request status indications, are all in
accordance with the IRQ6 interrupt settings.
When pins KIN7 to KIN0 are used as key-sense interrupt input pins, either low-level sensing or
falling-edge sensing must be designated as the interrupt sense condition for the corresponding
interrupt source (IRQ6).
5.3.2
There are 38 sources for internal interrupts from on-chip supporting modules, plus one software
interrupt source (address break).
5.3.3
Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of ICR. The situation when two or more modules
are set to the same priority, and priorities within a module, are fixed as shown in table 5.4.
For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If any one of these is set to
1, an interrupt request is issued to the interrupt controller.
The interrupt control level can be set by means of ICR.
The DTC can be activated by an FRT, TMR, SCI, or other interrupt request. When the DTC is
activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect.
Internal Interrupts
Interrupt Exception Vector Table
Rev. 4.00 Jun 06, 2006 page 115 of 1004
Section 5 Interrupt Controller
REJ09B0301-0400