HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 109
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HD64F2134FA20
Manufacturer Part Number
HD64F2134FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2134FA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2134FA20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD64F2134FA20V
Manufacturer:
RENESAS
Quantity:
201
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Notes: 1. Size refers to the operand size.
2.6.4
The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first four bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement.
Condition Field: Specifies the branching condition of Bcc instructions.
Type
Block data
transfer
instructions
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Basic Instruction Formats
B:
W: Word
L:
Byte
Longword
Instruction
EEPMOV.B
EEPMOV.W
Size *
—
—
1
Function
if R4L
else next;
if R4
else next;
Block transfer instruction. Transfers the number of data
bytes specified by R4L or R4 from locations starting at
the address indicated by ER5 to locations starting at the
address indicated by ER6. After the transfer, the next
instruction is executed.
Repeat @ER5+
Until R4L = 0
Repeat @ER5+
Until R4 = 0
0 then
R4L–1
R4–1
0 then
Rev. 4.00 Jun 06, 2006 page 53 of 1004
R4
R4L
@ER6+
@ER6+
REJ09B0301-0400
Section 2 CPU
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