HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 594

• Manufacturer Part Number: HD64F2134FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2134FA20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 17 Host Interface [H8S/2138 Group]
only when register IDR1 is accessed using CS1. Slave logic decodes the commands input from the
host processor. When an H'D1 host command is detected, bit 1 of the data following the host
command is output from the GA20 output pin. This operation does not depend on firmware or
interrupts, and is faster than the regular processing using interrupts. Table 17.7 lists the conditions
that set and clear GA20 (P81). Figure 17.2 shows the GA20 output in flowchart form. Table 17.8
indicates the GA20 output signal values.
Table 17.7 GA20 (P81) Set/Clear Timing
Pin Name
GA20 (P81) Rising edge of the host’s write signal
Rev. 4.00 Jun 06, 2006 page 538 of 1004
REJ09B0301-0400
Setting Condition
(IOW) when bit 1 of the written data is 1
and the data follows an H'D1 host
command
No
No
Figure 17.2 GA20 Output
Write bit 1 of data byte
to DR bit of P81/GA20
Wait for next byte
H'D1 command
Data byte?
received?
Start
Yes
Yes
Host write
Host write
Clearing Condition
Rising edge of the host’s write signal
(IOW) when bit 1 of the written data is 0
and the data follows an H'D1 host
command
Also, when bit FGA20E in HICR is cleared
to 0