HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 589

• Manufacturer Part Number: HD64F2134FA20
• Description: IC H8S MCU FLASH 128K 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of HD64F2134FA20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

17.2.8
ODR2 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register
to the host processor. The ODR2 contents are output on the host data bus when HA0 is low, CS2
is low, and IOR is low.
The initial values of ODR2 after a reset and in standby mode are undetermined.
17.2.9
STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3,
1, and 0 are read-only bits to both the host and slave processors.
STR2 is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D D D D ): Receives the HA0 input when the host processor writes to IDR2,
and indicates whether IDR2 contains data or a command.
Bit 3
C/D D D D
0
1
Bit
Initial value
Slave Read/Write
Host Read/Write
Bit
Initial value
Slave Read/Write
Host Read/Write
Note: * Only 0 can be written, to clear the flag.
Output Data Register 2 (ODR2)
Status Register 2 (STR2)
Description
Contents of input data register (IDR2) are data
Contents of input data register (IDR2) are a command
ODR7
DBU
R/W
R/W
—
R
R
7
7
0
ODR6
R/W
DBU
R/W
—
R
6
R
6
0
ODR5
R/W
DBU
R/W
—
R
5
R
5
0
ODR4
R/W
DBU
R/W
—
R
4
R
4
0
Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 533 of 1004
ODR3
R/W
C/D
—
R
R
R
3
3
0
ODR2
DBU
R/W
R/W
—
R
R
2
2
0
REJ09B0301-0400
ODR1
R/W
IBF
—
R
R
R
1
1
0
(Initial value)
R/(W) *
ODR0
OBF
R/W
—
R
R
0
0
0